{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024574","sets":["1164:1579:1701:1702"]},"path":["1702"],"owner":"1","recid":"24574","title":["マルチプロセッサ・システムのフォールトトレラント結合方式について"],"pubdate":{"attribute_name":"公開日","attribute_value":"1990-11-30"},"_buckets":{"deposit":"bb01ec64-5850-4274-9ce1-35d1f7d6a524"},"_deposit":{"id":"24574","pid":{"type":"depid","value":"24574","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"マルチプロセッサ・システムのフォールトトレラント結合方式について","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチプロセッサ・システムのフォールトトレラント結合方式について"},{"subitem_title":"A Method of Fault Tolerant Communication in a Multi - processor System","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1990-11-30","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"防衛大学校情報工学科"},{"subitem_text_value":"防衛大学校情報工学科"},{"subitem_text_value":"防衛大学校情報工学科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Computer Science, The National Defense Academy","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, The National Defense Academy","subitem_text_language":"en"},{"subitem_text_value":"Department of Computer Science, The National Defense Academy","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24574/files/IPSJ-ARC90064004.pdf"},"date":[{"dateType":"Available","dateValue":"1992-11-30"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC90064004.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"e2d2afa2-f796-4832-b39e-55515717ee46","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1990 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"田中, 徳彦"},{"creatorName":"黒川, 恭一"},{"creatorName":"古賀, 義亮"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Norihiko, Tanaka","creatorNameLang":"en"},{"creatorName":"Takakazu, Kurokawa","creatorNameLang":"en"},{"creatorName":"Yoshiaki, Koga","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"マルチプロセッサ・システムのプロセッサ間結合方式について、パイプライン並列処理を例として相互結合ネットワークとその結合回路（バンクメモリ結合回路）を提案し、フォールトトレラント・パイプライン処理システムを構成する。バンクメモリ結合回路によるマルチプロセッサ・システムは、結合しているプロセッサの機能障害を検出することができるため、フォールトトレラント化に有利な結合回路であるばかりでなく、パイプライン処理のように大量のデータを一方向に転送するアプリケーションに対して従来の結合回路の問題点を改善する。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper proposes a new fault tolerant communication method and three new interconnection networks to construct a multi-processor system for a pipeline processing. The proposed communication scheme using bank memory switching technique has an advantage to make a fault tolerant pipeline system so that it can detect any failure caused in processing elements of the system. In addition, it can overcome the conventional problems caused in interconnection circuits to flow data with one way direction such as a pipeline processing.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"8","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"1990-11-30","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"96(1990-ARC-064)","bibliographicVolumeNumber":"1990"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":24574,"updated":"2025-01-22T19:51:44.433469+00:00","links":{},"created":"2025-01-18T22:55:40.617239+00:00"}