{"updated":"2025-01-22T19:53:01.281347+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024515","sets":["1164:1579:1688:1693"]},"path":["1693"],"owner":"1","recid":"24515","title":["5ポートレジスタファイルを用いたVLIW型計算機KIDOCH"],"pubdate":{"attribute_name":"公開日","attribute_value":"1991-07-19"},"_buckets":{"deposit":"e1f8f052-5400-45b2-958a-c1ad0ad61c62"},"_deposit":{"id":"24515","pid":{"type":"depid","value":"24515","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"5ポートレジスタファイルを用いたVLIW型計算機KIDOCH","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"5ポートレジスタファイルを用いたVLIW型計算機KIDOCH"},{"subitem_title":"VLIW COMPUTER KIDOCH USING 5 PORT REGISTER FILES","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1991-07-19","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東北大学大型計算機センター"},{"subitem_text_value":"千葉工業大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Computer Center, Tohoku University","subitem_text_language":"en"},{"subitem_text_value":"Chiba Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24515/files/IPSJ-ARC91089011.pdf"},"date":[{"dateType":"Available","dateValue":"1993-07-19"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC91089011.pdf","filesize":[{"value":"746.2 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"e183709e-015d-46fa-96c4-2b33d93a7d32","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1991 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"安倍, 正人"},{"creatorName":"城戸, 健一"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masato, Abe","creatorNameLang":"en"},{"creatorName":"Ken-Iti, Kido","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"現状のVLIW型の計算機の問題として、入力データのポート数が1つしか無いことがあげられる。すなわち、たとえ演算器が複数あってもほとんどの計算において実際に動作する演算器は1つだけということになり、パフォーマンスが良くない。そこで、我々は複数のデータキャッシュをサポートするVLIW型計算機KIDOCHを開発中である。具体的には2つのデータキャッシュをサポートし、さらに5ポートレジスタファイルを用いてキャッシュ間のコヒーレンスも保つようにしている。また、この5ポートレジスタファイルはMMUのTLBおよび汎用のレジスタファイルとしても効果的に用いられている。さらに、これらの機能を有効に使うためのCコンパイラについても特にループ展開について詳しく述べている。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper describes the architecture of a VLIW computer, KIDOCH IV, with a two-port data memory unit using 5-port register files. The two-port data memory with a 4 GB addressing space is managed by the two data memory management units using tire two 5-port register files and two 64 page data cache memory units. The outputs also have the information whether or not the write access was performed through a different data memory port. This allows an easy implementation of a C compiler supporting two-port data memory.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"80","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"75","bibliographicIssueDates":{"bibliographicIssueDate":"1991-07-19","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"64(1991-ARC-089)","bibliographicVolumeNumber":"1991"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:55:37.972353+00:00","id":24515,"links":{}}