{"created":"2025-01-18T22:55:37.659623+00:00","updated":"2025-01-22T19:52:50.645551+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024508","sets":["1164:1579:1688:1693"]},"path":["1693"],"owner":"1","recid":"24508","title":["スーパースカラ・マイクロプロセッサOHMEGAにおける動的ハザード解消機構と高速化手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1991-07-19"},"_buckets":{"deposit":"5f5b4bba-de6c-46e7-a799-eea6fa808f6d"},"_deposit":{"id":"24508","pid":{"type":"depid","value":"24508","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"スーパースカラ・マイクロプロセッサOHMEGAにおける動的ハザード解消機構と高速化手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"スーパースカラ・マイクロプロセッサOHMEGAにおける動的ハザード解消機構と高速化手法"},{"subitem_title":"Dynamic Hazard Resolution Mechanism and Architectural Improvement of Superscalar Microprocessor OHMEGA","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1991-07-19","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"松下電器産業（株）半導体研究センター"},{"subitem_text_value":"松下電器産業（株）半導体研究センター"},{"subitem_text_value":"松下電器産業（株）半導体研究センター"},{"subitem_text_value":"松下電器産業（株）半導体研究センター"},{"subitem_text_value":"松下電器産業（株）半導体研究センター"},{"subitem_text_value":"松下電器産業（株）半導体研究センター"},{"subitem_text_value":"松下電器産業（株）半導体研究センター"},{"subitem_text_value":"松下電器産業（株）半導体研究センター"},{"subitem_text_value":"松下電器産業（株）半導体研究センター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Semiconductor Research Center, Matsushita Electric Industrial Co., Lｔd.","subitem_text_language":"en"},{"subitem_text_value":"Semiconductor Research Center, Matsushita Electric Industrial Co., Lｔd.","subitem_text_language":"en"},{"subitem_text_value":"Semiconductor Research Center, Matsushita Electric Industrial Co., Lｔd.","subitem_text_language":"en"},{"subitem_text_value":"Semiconductor Research Center, Matsushita Electric Industrial Co., Lｔd.","subitem_text_language":"en"},{"subitem_text_value":"Semiconductor Research Center, Matsushita Electric Industrial Co., Lｔd.","subitem_text_language":"en"},{"subitem_text_value":"Semiconductor Research Center, Matsushita Electric Industrial Co., Lｔd.","subitem_text_language":"en"},{"subitem_text_value":"Semiconductor Research Center, Matsushita Electric Industrial Co., Lｔd.","subitem_text_language":"en"},{"subitem_text_value":"Semiconductor Research Center, Matsushita Electric Industrial Co., Lｔd.","subitem_text_language":"en"},{"subitem_text_value":"Semiconductor Research Center, Matsushita Electric Industrial Co., Lｔd.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24508/files/IPSJ-ARC91089004.pdf"},"date":[{"dateType":"Available","dateValue":"1993-07-19"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC91089004.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"6bfd67ac-e5a7-45d8-aa8f-195563e4a844","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1991 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"中島, 雅逸"},{"creatorName":"中野, 拓"},{"creatorName":"中倉, 康浩"},{"creatorName":"吉田, 忠弘"},{"creatorName":"後井, 良之"},{"creatorName":"中居, 祐二"},{"creatorName":"瀬川, 礼二"},{"creatorName":"岸田, 武"},{"creatorName":"廉田, 浩"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masaitsu, Nakajima","creatorNameLang":"en"},{"creatorName":"Hiraku, Nakano","creatorNameLang":"en"},{"creatorName":"Yasuhiro, Nakakura","creatorNameLang":"en"},{"creatorName":"Tadahiro, Yoshida","creatorNameLang":"en"},{"creatorName":"Yoshiyuki, Goi","creatorNameLang":"en"},{"creatorName":"Yuji, Nakai","creatorNameLang":"en"},{"creatorName":"Reiji, Segawa","creatorNameLang":"en"},{"creatorName":"Takeshi, Kishida","creatorNameLang":"en"},{"creatorName":"Hiroshi, Kadota","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"数値計算分野を主たるアプリケーションとする次世代超高速並列計算機ADENART?Hのプロセッシング・エレメントとしてスーパースカラ・マイクロプロセッサOHMEGAを開発した。OHMEGAはスーパースカラ方式と呼ばれる命令レベルの並列実行方式を採用し、1クロックサイクルごとに同時に2命令を並列実行する。さらにout?of?orderの命令実行、データ依存関係に関わる動的なハザード解消、条件コード先見によるノン?ペナルティ条件分岐等の特徴を有することにより、高い実行性能を実現する。本報告では、OHMEGAにおける動的ハザード解消機構であるDTC(rectly　Tag　Compa)方式と、分岐命令実行および、外部メモリアクセスに関しての高速化手法ついて述べる。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"We have developed a VLSI superscalar microprocessor as a processing element for next generation massively parallel computer system ADENART-H, and it's called OHMEGA processor. OHMEGA processor adopts superscalar architecture that executes two scalar instructions at each clock cycle, and has some architectural features, out-of-order execution of instructions, dynamic hazard resolution mechanism (DTC method), and non-penalty conditional branch execution. OHMEGA processor realizes a very high performance by taking advantage of these architectural improvement. This paper describes the architectural features of OHMEGA processor, dynamic hazard resolution mechanism (DTC method) and architectural improvement for conditional branch execution and external memory access operation.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"31","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"25","bibliographicIssueDates":{"bibliographicIssueDate":"1991-07-19","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"64(1991-ARC-089)","bibliographicVolumeNumber":"1991"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":24508,"links":{}}