{"updated":"2025-01-22T19:56:12.508558+00:00","links":{},"id":24397,"created":"2025-01-18T22:55:32.728514+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024397","sets":["1164:1579:1680:1682"]},"path":["1682"],"owner":"1","recid":"24397","title":["ALUの例外処理の高速化手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1992-10-22"},"_buckets":{"deposit":"86ccb612-f9f0-4370-9262-cdc1cd8cae6a"},"_deposit":{"id":"24397","pid":{"type":"depid","value":"24397","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"ALUの例外処理の高速化手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ALUの例外処理の高速化手法"},{"subitem_title":"A methodology for a high - speed ALU with exception circuitry","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1992-10-22","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"NECマイクロエレクトロニクス研究所システムULSI研究部"},{"subitem_text_value":"NECマイクロエレクトロニクス研究所システムULSI研究部"},{"subitem_text_value":"NECマイクロエレクトロニクス研究所システムULSI研究部"},{"subitem_text_value":"中央大学理工学部情報工学科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation","subitem_text_language":"en"},{"subitem_text_value":"System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation","subitem_text_language":"en"},{"subitem_text_value":"System ULSI Research Laboratory, Microelectronics Research Laboratories, NEC Corporation","subitem_text_language":"en"},{"subitem_text_value":"Department of Information and System Engineering, Faculty of Science and Engineering, Chuo University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24397/files/IPSJ-ARC92096010.pdf"},"date":[{"dateType":"Available","dateValue":"1994-10-22"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC92096010.pdf","filesize":[{"value":"1.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"1190a764-30ba-48ac-a7e8-03cd1f3234f3","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1992 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"鈴木, 一正"},{"creatorName":"山品正勝"},{"creatorName":"山田, 八郎"},{"creatorName":"榎本, 忠儀"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kazumasa, Suzuki","creatorNameLang":"en"},{"creatorName":"Masakazu, Yamashina","creatorNameLang":"en"},{"creatorName":"Hachiro, Yamada","creatorNameLang":"en"},{"creatorName":"Tadayoshi, Enomoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"マイクロプロセッサに用いられる演算器は，演算以外にも状態フラグの出力や演算結果の補正等の例外処理を行う．そのため，演算器を高速化するためには例外処理の回路を含めて高速化する必要がある．例外処理を高速化するためには，例外処理回路を演算器回路と並列にする方法が効果的である．そこで，例外処理回路の構成例として，桁上げ選択法を応用した零フラグ検出回路と，比較器を用いたオーバフロー補正回路を提案した．この回路を用いたオーバフロー補正機能と零フラグ検出機能を持つ16?bit加算器について，並列化の効果を見積ったところ，0．5μmCMOSで処理時間が4．20nsから3．05nsに改善され，演算時間が25%短縮された．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"An arithmetic unit in a microprocessor not only has arithmetic operations but also has exception handling, for example flag detection and the result value correction. A parallel architecture for an arithmetic circuitry and an exception handling circuitry reduces the time required for exception handling, thus making the arithmetic unit faster. Examples of exception circuitry, a zero-flag detector and an overflow corrector are shown. These two circuitries reduce the operation time for a 16-bit adder with the zero-flag detection and overflow correction functions from 4.20ns to 3.05ns on a 0.5 micron CMOS technology.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"80","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"73","bibliographicIssueDates":{"bibliographicIssueDate":"1992-10-22","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"82(1992-ARC-096)","bibliographicVolumeNumber":"1992"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}