{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024286","sets":["1164:1579:1673:1674"]},"path":["1674"],"owner":"1","recid":"24286","title":["ASIP向きハードウェア/ソフトウェア・コデザインシステムPEAS - Iにおけるデータパス部の最適化手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"1993-12-16"},"_buckets":{"deposit":"8ca5fd31-5c02-4d34-9389-7448958df5cd"},"_deposit":{"id":"24286","pid":{"type":"depid","value":"24286","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"ASIP向きハードウェア/ソフトウェア・コデザインシステムPEAS - Iにおけるデータパス部の最適化手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ASIP向きハードウェア/ソフトウェア・コデザインシステムPEAS - Iにおけるデータパス部の最適化手法"},{"subitem_title":"Datapath Optimization Methodology in PEAS - I : A Hardware/Software Codesign System for ASIP","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1993-12-16","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"豊橋技術科学大学情報工学系"},{"subitem_text_value":"豊橋技術科学大学情報工学系"},{"subitem_text_value":"豊橋技術科学大学情報工学系"},{"subitem_text_value":"SRA"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Toyohashi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"Toyohashi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"Toyohashi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"SRA","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24286/files/IPSJ-ARC93103021.pdf"},"date":[{"dateType":"Available","dateValue":"1995-12-16"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC93103021.pdf","filesize":[{"value":"1.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"62ed7712-827b-4c72-9d5c-73b540f796f2","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1993 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"本間, 啓道"},{"creatorName":"塩見, 彰睦"},{"creatorName":"今井, 正治"},{"creatorName":"引地, 信之"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yoshimichi, Honma","creatorNameLang":"en"},{"creatorName":"Akichika, Shiomi","creatorNameLang":"en"},{"creatorName":"Masaharu, Imai","creatorNameLang":"en"},{"creatorName":"Nobuyuki, Hikichi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"PEAS?Iは,ASIPを開発するためのハードウェア/ソフトウェア・コデザイン・システムであり,特定分野の応用プログラムをより高速に実行するCPUコアとそのCPUコアをターゲットとする応用プログラム開発環境を同時に生成するシステムである.本稿では,レジスタの個数を考慮した命令セットの最適化の手法について述べ,本手法を用いて生成したCPUコアが従来のCPUコアより高速に応用プログラムを実行できることを示す.また,応用プログラムから静的解析及び動的解析を用いて最適化に必要なデータを抽出する方法について述べる.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper describes the datapath optimization method in PEAS-I, which is a hardware/software codesign system for ASIP development. The PEAS-I system analyzes a set of application programs and associated data set, determines optimal instruction set, and then generates CPU core and application program development tools. A datapath of the generated CPU core consists of register file and computational modules. This method optimizes both the size of register file and the combination of computational modules. Using this method, a better design of the CPU core.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"166","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ(ARC)"}],"bibliographicPageStart":"159","bibliographicIssueDates":{"bibliographicIssueDate":"1993-12-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"111(1993-ARC-103)","bibliographicVolumeNumber":"1993"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":24286,"updated":"2025-01-22T19:59:23.742103+00:00","links":{},"created":"2025-01-18T22:55:27.780723+00:00"}