{"id":24188,"updated":"2025-01-22T20:01:28.958805+00:00","links":{},"created":"2025-01-18T22:55:23.472947+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024188","sets":["1164:1579:1665:1667"]},"path":["1667"],"owner":"1","recid":"24188","title":["関数型言語指向プロセッサアーキテクチャ"],"pubdate":{"attribute_name":"公開日","attribute_value":"1994-10-27"},"_buckets":{"deposit":"b7de8ab4-0aa6-413d-9588-cf54d94dc71c"},"_deposit":{"id":"24188","pid":{"type":"depid","value":"24188","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"関数型言語指向プロセッサアーキテクチャ","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"関数型言語指向プロセッサアーキテクチャ"},{"subitem_title":"Processor Architecture for Functional Programs","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1994-10-27","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"奈良先端科学技術大学院大学情報科学研究科"},{"subitem_text_value":"奈良先端科学技術大学院大学情報科学研究科"},{"subitem_text_value":"奈良先端科学技術大学院大学情報科学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science Nara Institute of Science and Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24188/files/IPSJ-ARC94108012.pdf"},"date":[{"dateType":"Available","dateValue":"1996-10-27"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC94108012.pdf","filesize":[{"value":"1.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"402ba2fd-bdfb-4519-987a-4371c8e6f90b","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1994 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"田中, 哲也"},{"creatorName":"荒木, 啓二郎"},{"creatorName":"福田, 晃"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tetsuya, Tanaka","creatorNameLang":"en"},{"creatorName":"Keijiro, Araki","creatorNameLang":"en"},{"creatorName":"Akira, Fukuda","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"リダクション・マシンに用いるプロセッサとして、RISCアーキテクチャをベースにしたアーキテクチャを提案する。本アーキテクチャは、関数プログラムの格納領域としてオンチップ・スタックをプロセッサ内部に持つため、関数プログラムの高速なアクセスができ、複数のスタックとスタックへのポインタを実現する機構により、高速な関数評価を実現する。さらに、オンチップ・スタックを共有し、独立に動作可能なマルチ・パイプライン・ユニットにより、並行評価を行う機構を備えている。これらの特徴により、本プロセッサ・アーキテクチャは関数型言語を高速に実行する。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this paper, we propose a processor architecture for reduction machines which is based on a RISC architecture. The proposed architecture can access functional programs fast, using an on-chip-stack in the processor for storing functional programs. And, the architecture can evaluate functions fast using a mechanism supporting a multi-stack and its pointer-to-stack as the on-chip-stack. Furthermore, the architecture can evaluate functions in parallel using multi-pipeline which can run in independent each other and share an on-chip-stack. By these features, the architecture can execute functional programs fast.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"78","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"71","bibliographicIssueDates":{"bibliographicIssueDate":"1994-10-27","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"91(1994-ARC-108)","bibliographicVolumeNumber":"1994"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}