{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024088","sets":["1164:1579:1658:1659"]},"path":["1659"],"owner":"1","recid":"24088","title":["ASIP設計用ワークベンチPEAS - IIIの実現方法についての考察　－CPUアーキテクチャの分類とパラメタ化－"],"pubdate":{"attribute_name":"公開日","attribute_value":"1995-12-14"},"_buckets":{"deposit":"7e33d058-c46f-4469-b4d1-50126ec0abfd"},"_deposit":{"id":"24088","pid":{"type":"depid","value":"24088","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"ASIP設計用ワークベンチPEAS - IIIの実現方法についての考察　－CPUアーキテクチャの分類とパラメタ化－","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ASIP設計用ワークベンチPEAS - IIIの実現方法についての考察　－CPUアーキテクチャの分類とパラメタ化－"},{"subitem_title":"Observations on the Implementation of a Codesign Workbench PEAS - III for ASIP Design -Classification and Parameterization of CPU Architectures-","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1995-12-14","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"豊橋技術科学大学"},{"subitem_text_value":"豊橋技術科学大学"},{"subitem_text_value":"豊橋技術科学大学"},{"subitem_text_value":"豊橋技術科学大学"},{"subitem_text_value":"鶴岡工業高等専門学校"},{"subitem_text_value":"SRA"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Toyohashi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"Toyohashi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"Toyohashi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"Toyohashi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"Tsuruoka National College of Technology","subitem_text_language":"en"},{"subitem_text_value":"Software Research Associates Inc.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24088/files/IPSJ-ARC95115020.pdf"},"date":[{"dateType":"Available","dateValue":"1997-12-14"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC95115020.pdf","filesize":[{"value":"432.0 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"3013c1e1-ecf0-4cab-b961-bac9e8b15b72","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1995 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"片岡, 健二"},{"creatorName":"塩見, 彰睦"},{"creatorName":"今井, 正治"},{"creatorName":"青山, 義弘"},{"creatorName":"佐藤, 淳"},{"creatorName":"引地, 信之"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kenji, Kataoka","creatorNameLang":"en"},{"creatorName":"Akichika, Shiomi","creatorNameLang":"en"},{"creatorName":"Masaharu, Imai","creatorNameLang":"en"},{"creatorName":"Yoshihiro, Aoyama","creatorNameLang":"en"},{"creatorName":"Jun, Sato","creatorNameLang":"en"},{"creatorName":"Nobuyuki, Hikichi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"ASICのコデザインに関する研究は種々行なわれているが，現状ではコデザインで用いられるCPUアーキテクチャがかなり限定されているのが現状である．しかし実際には対象となるアプリケーションの分野に応じてCPUのアーキテクチャを変化させた方が良い結果が得られると考えられる．本稿ではASIP設計用ワークベンチであるPEAS?IIIシステムのアーキテクチャ記述入力系のプロトタイピングを行なった結果を報告する．特に様々なアーキテクチャに対応できる手法について述べる．また実現の際に得られた所見についても述べる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In many HW/SW codesign system can handle very limited architecture class of CPU. However, application specific CPU would have better performance, HW cost, and power consumption trade-off. This paper describes the prototype implementation PEAS-III, a HW/SW codesign workbench for ASIP (Application Specific Integrated Processor) design.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"126","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"121","bibliographicIssueDates":{"bibliographicIssueDate":"1995-12-14","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"119(1995-ARC-115)","bibliographicVolumeNumber":"1995"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":24088,"updated":"2025-01-22T20:04:19.885631+00:00","links":{},"created":"2025-01-18T22:55:19.066028+00:00"}