{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00024067","sets":["1164:1579:1651:1657"]},"path":["1657"],"owner":"1","recid":"24067","title":["FPGAによる関数型言語向きアーキテクチャを持つプロセッサの実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"1996-01-26"},"_buckets":{"deposit":"08c12fc8-b6d8-47cb-9d87-b8c37cc01739"},"_deposit":{"id":"24067","pid":{"type":"depid","value":"24067","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"FPGAによる関数型言語向きアーキテクチャを持つプロセッサの実装","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAによる関数型言語向きアーキテクチャを持つプロセッサの実装"},{"subitem_title":"Implementation of a processor for Functional Languages on FPGA","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1996-01-26","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院工学系研究科"},{"subitem_text_value":"東京大学大学院工学系研究科"},{"subitem_text_value":"東京大学大学院工学系研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Engineering, University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Engineering, University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Engineering, University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/24067/files/IPSJ-ARC95116010.pdf"},"date":[{"dateType":"Available","dateValue":"1998-01-26"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC95116010.pdf","filesize":[{"value":"537.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"fc57e57c-7029-418c-8add-7bfc4eae4e01","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1996 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"柳井, 啓司"},{"creatorName":"田中, 哲朗"},{"creatorName":"武市, 正人"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Keiji, Yanai","creatorNameLang":"en"},{"creatorName":"Tetsuro, Tanaka","creatorNameLang":"en"},{"creatorName":"Masato, Takeichi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"関数型言語向きアーキテクチャを持つプロセッサを，1万ゲート相当のFPGAを用いて実現した．本プロセッサは通常命令を実行するノーマルモードと関数型言語実行のためのリダクションモードの2種類の実行モードを持つ．リダクションモードでの実行を使用頻度の高い5つコンビネータにとどめ，他のコンビネータをノーマルモードで実行するという方針で設計をした結果，少量のハードウェアの追加で製作でき，ノーマルモードのみの実行と比較して5倍程度の速度の向上が確認された．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A processor for functional languages was implemented on a Field Programmable Gate Array (FPGA) with 10 thousand gates. This processor has two execution modes, \"normal mode\" for execution of normal instructions and \"reduction mode\" for reduction of combinators. The design of this processor is to execute five frequently used combinators in reduction mode and others in normal mode. Combination of normal mode and reduction mode enables the processor to execute functional programs about five times as fast as that only with normal mode.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"60","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"55","bibliographicIssueDates":{"bibliographicIssueDate":"1996-01-26","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"13(1995-ARC-116)","bibliographicVolumeNumber":"1996"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":24067,"updated":"2025-01-22T20:04:49.679864+00:00","links":{},"created":"2025-01-18T22:55:18.138906+00:00"}