{"created":"2025-01-19T01:44:45.484199+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00240521","sets":["1164:2036:11466:11785"]},"path":["11785"],"owner":"44499","recid":"240521","title":["Double Diffusion Break FinFETプロセスにおける面積ペナルティを軽減するセル内トランジスタ再配置法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-11-05"},"_buckets":{"deposit":"679ec6f4-010a-4a2c-b836-fda8d22e33c0"},"_deposit":{"id":"240521","pid":{"type":"depid","value":"240521","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"Double Diffusion Break FinFETプロセスにおける面積ペナルティを軽減するセル内トランジスタ再配置法","author_link":["659978","659981","659980","659979"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Double Diffusion Break FinFETプロセスにおける面積ペナルティを軽減するセル内トランジスタ再配置法"},{"subitem_title":"Area Penalty Mitigation by Inter-cell Transistor Reordering in Double Diffusion Break FinFET Process","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2024-11-05","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学大学院情報生産システム研究科"},{"subitem_text_value":"早稲田大学大学院情報生産システム研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information, Production and System, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information, Production and System, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/240521/files/IPSJ-SLDM24207039.pdf","label":"IPSJ-SLDM24207039.pdf"},"date":[{"dateType":"Available","dateValue":"2026-11-05"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM24207039.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"e84d3157-72a1-4f01-8e9d-d6fd7595d62a","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"西澤, 真一"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"木村, 晋二"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shinichi, Nishizawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Shinji, Kimura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本論文では Double Diffusion Break FinFET プロセスにおける面積ペナルティを軽減させるための，セル内のトランジスタの再配置法について述べる．第一世代の FinFET プロセスでは隣接セル間のリーク電流を遮断するために，Double Diffusion Break が必要であったが，2 つのダミートランジスタが必要であり面積オーバーヘッドが大きい課題があった．本論文ではセル内のトランジスタ配置を変更する事で，Double Diffusion Break が必要なルールにおいて積極的に Single Diffusion Break を適用する事で，セル内の面積ペナルティを削減する．ベンチマーク回路による実験の結果，提案方法を用いる事で平均的に 4.4% 回路面積を削減することがで来た．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper proposes standard cell layout style and transistor reordering algorithm to reduce the area penalty in the double-diffusion break FinFET process. First generation of FinFET process technology requires a double-diffusion break to shutdown leakage current under the dummy gate, however it need two the dummy gates at the cell edge and requires large area. This penalty can be mitigated by sharing the common VDD/VSS diffusions at neighbour cells to reduce the use of double diffusion break. We propose a FinFET cell layout style and transistor reorder algorithm which shares same VDD/VSS nodes can be shared with adjacent cells. Experimental result show that the proposed cell library with new layout style and reordering algorithm achieves 4.40% area reduction in average. I.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2024-11-05","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"39","bibliographicVolumeNumber":"2024-SLDM-207"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":240521,"updated":"2025-01-19T07:57:13.584399+00:00","links":{}}