{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00240501","sets":["1164:2036:11466:11785"]},"path":["11785"],"owner":"44499","recid":"240501","title":["PVTコーナーや要求特性に対応したベイズ最適化によるLDOサイジング"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-11-05"},"_buckets":{"deposit":"1fb15cd3-a940-4513-93a8-ca9f241e69d1"},"_deposit":{"id":"240501","pid":{"type":"depid","value":"240501","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"PVTコーナーや要求特性に対応したベイズ最適化によるLDOサイジング","author_link":["659878","659876","659877","659875"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"PVTコーナーや要求特性に対応したベイズ最適化によるLDOサイジング"},{"subitem_title":"LDO sizing using Bayesian optimization handling PVT corner and requirement","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2024-11-05","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"群馬大学"},{"subitem_text_value":"京都工芸繊維大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Gunma University","subitem_text_language":"en"},{"subitem_text_value":"Kyoto Institude of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/240501/files/IPSJ-SLDM24207019.pdf","label":"IPSJ-SLDM24207019.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM24207019.pdf","filesize":[{"value":"985.4 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"1080af74-4434-4685-a660-20ed8826cbfb","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"増渕, 剛"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"高井, 伸和"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tsuyohi, Masubuchi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Nobukazu, Takai","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"アナログ集積回路設計では，常に手戻りが発生してしまうリスクを抱えている．予期せぬ設計の手戻りは，要求特性の細かな設定や，プロセスばらつきなどの影響を受けない設計により発生確率を下げることができる．本論文では，より細かな要求特性，PVT コーナー条件を組み込んだ自動サイジングを実装することで，ユーザーが求める特性を満たす回路を自動設計する手法を提案する．TSMC65nm プロセスの LDO 回路において，9 個の PVTコーナー条件と 8 個の要求特性を全て満たすようなサイジングをベイズ最適化を用いて行った結果，設計者が要求した特性を全て満たす素子値を得ることに成功した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In analog integrated circuit design, there is always a risk of redesign. The probability of unexpected design rework can be reduce by detailed design of required characteristics and design that is not affected by process variations. Therefore, by implementing automatic sizing that incorporates more detailed required characteristics and PVT corner conditions, we suggest a method of automatic design that satisfied satisfied all of the characteristics required by the designer. For an LDO circuit on the TSMC 65nm process, 9 PVT corner conditions, 8 required charactics, and using Bayesian optimization, we performed to obtain element value that satisfied all of the characteristics required by the designer.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"4","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2024-11-05","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"19","bibliographicVolumeNumber":"2024-SLDM-207"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":240501,"updated":"2025-01-19T07:57:36.048647+00:00","links":{},"created":"2025-01-19T01:44:43.594846+00:00"}