{"updated":"2025-01-19T07:57:45.079844+00:00","links":{},"created":"2025-01-19T01:44:42.840685+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00240493","sets":["1164:2036:11466:11785"]},"path":["11785"],"owner":"44499","recid":"240493","title":["FPGAによる疎行列計算用CRS形式変換の高速化"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-11-05"},"_buckets":{"deposit":"f6b16156-2fca-4ad2-a936-87c942c390f5"},"_deposit":{"id":"240493","pid":{"type":"depid","value":"240493","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"FPGAによる疎行列計算用CRS形式変換の高速化","author_link":["659827","659830","659829","659828"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAによる疎行列計算用CRS形式変換の高速化"},{"subitem_title":"Accelerating CRS Format Conversion for Sparse Matrix Computation with FPGA","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2024-11-05","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"筑波大学システム情報工学研究群情報理工学位プログラム"},{"subitem_text_value":" 筑波大学システム情報系情報工学域"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Science and Technology Degree Programs in Systems and Information Engineering, University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"Institute of Systems and Information Engineering, University of Tsukuba","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/240493/files/IPSJ-SLDM24207011.pdf","label":"IPSJ-SLDM24207011.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM24207011.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"1894b952-5221-43be-bd1e-a6ebfdb1dce9","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"横野, 智也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山口, 佳樹"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tomoya, Yokono","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yoshiki, Yamaguchi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"疎行列ベクトル積 (SpMV) は科学技術計算において多用される重要な基本演算である．SpMV 計算のためには格納形式として CRS (Compressed Row Storage) 形式が一般的に用いられ，この形式変換を含めた全体の演算性能を向上させることが重要である．本稿では，CRS 形式変換部分の演算に着目し FPGA による高速化の可能性について議論する．CRS 形式変換用の演算回路を設計し，AMD 社の Alveo U280 FPGA に実装を行った．実装した CRS 変換回路はシミュレーションにおいて，問題サイズが大きいものに関してはナイーブな C 言語実装に対して約 6 倍， SciPy に対して約 17.2 倍，PETSc に対して約 8.2 倍の高速化を確認した．また，DMA や FPGA 上の内部メモリを含めた FPGA システムにおいては impcol_b のデータセットにおいて，ナイーブな C 言語実装に対して約 0.13 倍， SciPy に対して約 0.99 倍，PETSc に対して約 1.96 倍となることを確認した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The sparse matrix-vector multiplication (SpMV) is an important basic operation that is frequently used in scientific and engineering calculations. The CRS (Compressed Row Storage) format is commonly used as the storage format for SpMV calculations, and it is important to improve the performance of the overall calculation, including this format conversion. In this paper, we focus on CRS format conversion and discuss the possibility of speeding up the calculation using FPGAs. We designed an arithmetic circuit for CRS format conversion and implemented it on AMD Alveo U280 FPGA. The implemented CRS conversion circuit was confirmed to be approximately 6 times faster than the naive C implementation, approximately 17.2 times faster than SciPy and approximately 8.2 times faster than PETSc for large problem sizes in the simulation. In the FPGA system including DMA and internal memory on the FPGA, the speed-up was confirmed to be approximately 0.13 times faster than the naive C implementation, approximately 0.99 times faster than SciPy and approximately 1.96 times faster than PETSc for the impcol_b data set.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2024-11-05","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"11","bibliographicVolumeNumber":"2024-SLDM-207"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":240493}