{"id":240486,"updated":"2025-01-19T07:57:52.734819+00:00","links":{},"created":"2025-01-19T01:44:42.185796+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00240486","sets":["1164:2036:11466:11785"]},"path":["11785"],"owner":"44499","recid":"240486","title":["eFPGA IP向けPAE Cellを用いた新クラスタ構造およびクラスタリング手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-11-05"},"_buckets":{"deposit":"769c11fc-0c23-4186-8a78-3141ac7cadf6"},"_deposit":{"id":"240486","pid":{"type":"depid","value":"240486","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"eFPGA IP向けPAE Cellを用いた新クラスタ構造およびクラスタリング手法","author_link":["659789","659790","659784","659788","659787","659791","659785","659786"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"eFPGA IP向けPAE Cellを用いた新クラスタ構造およびクラスタリング手法"},{"subitem_title":"New Cluster Architecture and Clustering Method Using PAE Cells for eFPGA IP","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2024-11-05","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"熊本大学大学院自然科学教育部"},{"subitem_text_value":"熊本大学大学院自然科学教育部"},{"subitem_text_value":"熊本大学半導体・デジタル研究教育機構"},{"subitem_text_value":"熊本大学半導体・デジタル研究教育機構"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kumamoto University Graduate School of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Kumamoto University Graduate School of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Kumamoto University Research and Education Institute for Semiconductors and Informatics","subitem_text_language":"en"},{"subitem_text_value":"Kumamoto University Research and Education Institute for Semiconductors and Informatics","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/240486/files/IPSJ-SLDM24207004.pdf","label":"IPSJ-SLDM24207004.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM24207004.pdf","filesize":[{"value":"2.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"2ee3631d-2bd5-42b6-b82d-78c97fcd83dd","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"岩崎, 凌大"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"佐々木, 龍也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"瀬戸, 謙修"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯田, 全広"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ryo, Iwasaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tatsuya, Sasaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kenshu, Seto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masahiro, Iida","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"eFPGA IP の新論理セルとして，PAE Cell が提案されている．PAE Cell は一般的な LUT を用いた論理セルよりも構成メモリが少なく，多出力が可能であるという特徴がある．一方，クラスタ構造内のLCB（Local Connection Block）はクロスバーで作られており，入力数が増えると 2 のべき乗でスイッチ数が増える．したがって，多出力の PAE Cell では外部入力が同じでも，フィードバック入力が増えるため，クラスタの回路面積拡大が懸念される．本研究では，クラスタの面積増加を抑制するために，新クラスタ構造とクラスタリング手法を提案し，評価を行う．結果として，新クラスタ構造と提案クラスタリング手法を使用することで構成メモリ数を最大 38% の削減を行うことができた．また新クラスタに提案クラスタリング手法を使用することで，クラスタ数をフルクロスバーと同程度にすることができ，クラスタ数増加を抑えることが可能となった．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The PAE Cell has been proposed as a new logic cell for eFPGA IP. The PAE Cell is characterized by requiring fewer configuration memories than general LUT-based logic cells while also supporting multiple outputs. On the other hand, the Local Connection Block (LCB) within the cluster structure is built using a crossbar, and the number of switches increases exponentially as the number of inputs increases. Therefore, in multi-output PAE Cells, even with the same external inputs, the increase in feedback inputs raises concerns about the expansion of the cluster’s circuit area. In this study, a new cluster structure and clustering method are proposed to suppress the increase in cluster area, and evaluations are performed. As a result, using the proposed cluster structure and clustering method, the number of configuration memories was reduced, achieving up to 38% reduction. Furthermore, the proposed clustering method, when applied to the new cluster structure, made it possible to maintain the number of clusters at a similar level to that of full crossbar clusters, effectively mitigating the increase in the number of clusters.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2024-11-05","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"4","bibliographicVolumeNumber":"2024-SLDM-207"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}