@techreport{oai:ipsj.ixsq.nii.ac.jp:00024033,
 author = {松岡, 浩司 and 岡本, 一晃 and 廣野, 英雄 and 横田, 隆史 and 坂井, 修一 and Hiroshi, Matsuoka and Kazuaki, Okamoto and Hideo, Hirono and Takashi, Yokota and Shuichi, Sakai},
 issue = {80(1996-ARC-119)},
 month = {Aug},
 note = {並列実行モデルとプロセッサ間通信の観点から超並列計算機RWC?1の要素プロセッサの概要について述べる．RWC?1の要素プロセッサは通信と処理を融合し，かつ単純化したアーキテクチャであるRICA　(educed　Inter?processor　Communication　Architectur)を採用し，細粒度の並列処理を効率良く実行することができる．本稿では，スーパスカラプロセッサのデータパスを利用することによって現実的なコストでRICAを実装する方式を提案する．, From the view point of parallel execution models and inter-processor communication architecture, an overview of processor elements of massive parallel computer RWC-1 is discussed. RWC-1 processor elements adopt the RICA (Reduced Inter-processor Communication Architecture) in which communications and processing are fused and simplified to increase fine grain parallel execution efficiency. A 〓 effective implementation method for RICA which uses the data paths of conventional super-scalar processors are proposed.},
 title = {RWC - 1の要素プロセッサ　－細粒度並列処理機能の強化－},
 year = {1996}
}