{"created":"2025-01-19T01:44:02.387837+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00240067","sets":["6164:6165:7006:11799"]},"path":["11799"],"owner":"44499","recid":"240067","title":["LogicLocking による FPGA 回路の階層的な保護を目的とした回路設計情報難読化の提案"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-10-23"},"_buckets":{"deposit":"b8c05679-f37e-492c-a15a-126c3731fc8d"},"_deposit":{"id":"240067","pid":{"type":"depid","value":"240067","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"LogicLocking による FPGA 回路の階層的な保護を目的とした回路設計情報難読化の提案","author_link":["658134","658136","658135"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"LogicLocking による FPGA 回路の階層的な保護を目的とした回路設計情報難読化の提案"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGAアクセラレーション，LogicLocking，セキュリティ，難読化，ランダムLogicLocking","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2024-10-23","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"金沢工業大学"},{"subitem_text_value":"金沢工業大学"},{"subitem_text_value":"金沢工業大学"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/240067/files/IPSJ-DPSWS20240001.pdf","label":"IPSJ-DPSWS20240001.pdf"},"date":[{"dateType":"Available","dateValue":"2026-10-23"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DPSWS20240001.pdf","filesize":[{"value":"815.7 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"34"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"1c1057fd-bf96-43aa-9270-5c5b42a3b122","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"北川, 裕基"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"中沢, 実"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"河並, 崇"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本研究では，データセンタなどにおいてアクセラレーション用途としてインフラストラクチャ機能のハードウェアオフローディングが注目されてきている中で特に，FPGA に焦点を当て Bitstream のリバースエンジニアリングなどから回路の設計情報を保護するための階層的なセキュリティ保護を目的とする．難読化手法である LogicLocking を実装しサーバサイドにおける FPGA 活用におけるセキュリティを検討する．","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"第32回マルチメディア通信と分散処理ワークショップ論文集"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2024-10-23","bibliographicIssueDateType":"Issued"}}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":240067,"updated":"2025-01-19T08:05:53.134539+00:00","links":{}}