{"created":"2025-01-19T01:41:48.593208+00:00","updated":"2025-01-19T08:32:23.526504+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00238526","sets":["1164:2735:11468:11707"]},"path":["11707"],"owner":"44499","recid":"238526","title":["LSI詳細配線設計の並列処理効率化を指向した回路分割手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-08-29"},"_buckets":{"deposit":"040e123b-ee5d-4f84-91f1-1f8d6b40bb6f"},"_deposit":{"id":"238526","pid":{"type":"depid","value":"238526","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"LSI詳細配線設計の並列処理効率化を指向した回路分割手法","author_link":["653176","653177"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"LSI詳細配線設計の並列処理効率化を指向した回路分割手法"},{"subitem_title":"Circuit Partitioning Method for Parallel Processing of LSI Detailed Routing","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2024-08-29","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京農工大学工学府"},{"subitem_text_value":"東京農工大学工学府"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/238526/files/IPSJ-MPS24150006.pdf","label":"IPSJ-MPS24150006.pdf"},"date":[{"dateType":"Available","dateValue":"2026-08-29"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-MPS24150006.pdf","filesize":[{"value":"1.8 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"17"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"f7258dca-5487-45bd-979c-25b4eefa7990","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"小林, 大知"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"藤吉, 邦洋"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10505667","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8833","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"集積回路の配線設計は，接続すべき多数の端子が密集し複雑に絡み合っているため領域を分割し複数の領域で配線を並列に計算することは難しいとされている．しかし，配線領域に余裕がある場合には，FPGA の配線設計と同様の手法で並列処理が可能であることが示されているが，適切に領域を分割できないことが問題となっていた．従来の回路分割手法では，分割された領域をまたぐような配線を減少させることは可能であるが，領域ごとの配線に関わる計算時間が大きく偏り，最終的な計算時間が増加してしまうという課題があった．本研究では，解析的配置手法の考え方を利用し，線型計画法を用いて配線長が短くなるように 1 次元空間上に素子を並べ適切な位置で分割するという回路分割手法を提案する．計算機実験の結果，配線時間の偏りが減少する傾向がみられた．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告数理モデル化と問題解決（MPS）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2024-08-29","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"6","bibliographicVolumeNumber":"2024-MPS-150"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":238526,"links":{}}