{"updated":"2025-01-22T20:10:34.345402+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00023842","sets":["1164:1579:1639:1641"]},"path":["1641"],"owner":"1","recid":"23842","title":["OSCAR FORTRAN Compilerを用いたマルチグレイン並列性の評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"1998-08-05"},"_buckets":{"deposit":"12c8ec45-3f4a-4ca8-b27f-aab168d8500a"},"_deposit":{"id":"23842","pid":{"type":"depid","value":"23842","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"OSCAR FORTRAN Compilerを用いたマルチグレイン並列性の評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"OSCAR FORTRAN Compilerを用いたマルチグレイン並列性の評価"},{"subitem_title":"Evaluation of Multigrain Parallelism using OSCAR FORTRAN Compiler","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"1998-08-05","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学理工学部電気電子情報工学科"},{"subitem_text_value":"松下電器産業（株）"},{"subitem_text_value":"（株）東芝"},{"subitem_text_value":"早稲田大学理工学部電気電子情報工学科"},{"subitem_text_value":"早稲田大学理工学部電気電子情報工学科"},{"subitem_text_value":"早稲田大学理工学部電気電子情報工学科"},{"subitem_text_value":"早稲田大学理工学部電気電子情報工学科"},{"subitem_text_value":"（株）東芝"},{"subitem_text_value":"早稲田大学理工学部電気電子情報工学科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Department of Electrical Electronics and Computer Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Matsushita Electric Industrial Co., LTD.","subitem_text_language":"en"},{"subitem_text_value":"Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Department of Electrical Electronics and Computer Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Electrical Electronics and Computer Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Electrical Electronics and Computer Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Department of Electrical Electronics and Computer Engineering, Waseda University","subitem_text_language":"en"},{"subitem_text_value":"Matsushita Electric Industrial Co., LTD.","subitem_text_language":"en"},{"subitem_text_value":"Department of Electrical Electronics and Computer Engineering, Waseda University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/23842/files/IPSJ-ARC98130003.pdf"},"date":[{"dateType":"Available","dateValue":"2000-08-05"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC98130003.pdf","filesize":[{"value":"651.3 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"79e8b043-73d2-49ad-8008-da98f54f5538","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 1998 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"小幡, 元樹"},{"creatorName":"松井, 巌徹"},{"creatorName":"松崎, 秀則"},{"creatorName":"木村, 啓二"},{"creatorName":"稲石大祐"},{"creatorName":"宇治川, 泰史"},{"creatorName":"山本, 晃正"},{"creatorName":"岡本, 雅巳"},{"creatorName":"笠原, 博徳"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Motoki, Obata","creatorNameLang":"en"},{"creatorName":"Gantetsu, Matsui","creatorNameLang":"en"},{"creatorName":"Hidenori, Matsuzaki","creatorNameLang":"en"},{"creatorName":"Keiji, Kimura","creatorNameLang":"en"},{"creatorName":"Daisuke, Inaishi","creatorNameLang":"en"},{"creatorName":"Yasushi, Ujigawa","creatorNameLang":"en"},{"creatorName":"Terumasa, Yamamoto","creatorNameLang":"en"},{"creatorName":"Masami, Okamoto","creatorNameLang":"en"},{"creatorName":"Hironori, Kasahara","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"現在スーパーコンピュータは、数TFLOPSのピーク性能を持ち、今後も伸び続けると考えられるが、価格性能比、使い難さの問題から市場を拡大できないという問題を持っている。また、マイクロプロセッサにおいては、スーパースカラ、VLIW等で利用されている命令レベル並列性の限界が顕在化しており、次世代のプロセッサとして、シングルチップマルチプロセッサ(SCM)が注目されつつある。著者らは、SCM、サーバマシン、スーパーコンピュータの実効性能、すなわちコストパフォーマンス、使い易さを高めることを可能とするために、マルチグレイン自動並列化コンパイル手法を提案している。マルチグレイン並列処理とは、命令あるいはステートメントレベルの細粒度並列性、ループイタレーションレベルの中粒度並列性、サブルーチン・ループ・基本ブロックレベルの粗粒度並列性という、プログラムに内在する並列性を最大限に引き出す方式である。本論文では、Perfect Benchmarkの2次元流体解析プログラムARC2Dを例に、OSCARマルチグレインFORTRAN並列化Compilerを用いたマルチグレイン並列性利用の有効性を示す。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Currently, peak performances of supercomputers attain TFLOPS order. It seems that the peak performances will continue by increase. However, supercomputers have a problem that enlargement of the world is very difficult because of relatively low cost performance and difficulty of use. In microprocessor, limitations of extraction of instruction level parallelism being used by super scalar and VLIW architecture are getting clear and single chip multiprocessor is received much attention as one of next generation processor architechture. In order to improve effective performance or cost performance, and ease of use, the authors have been proposing a Multigrain Automatic Parallelizing Compilation scheme. The multigrain parallel processing is a method which extract all parallelism from a program, such as coarse grain parallelism among subroutines, loops, and basic blocks, medium grain parallelism among loop iterations, and fine grain parallelism among instructions and statements. This paper shows effectiveness of multigrain parallel processing using OSCAR multigrain FORTRAN parallelization compiler using fluid flow problem solver ARC2D(Perfect Benchmark) as an example.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"18","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"13","bibliographicIssueDates":{"bibliographicIssueDate":"1998-08-05","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"70(1998-ARC-130)","bibliographicVolumeNumber":"1998"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:55:08.572464+00:00","id":23842,"links":{}}