{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00238269","sets":["6164:6165:7651:11699"]},"path":["11699"],"owner":"44499","recid":"238269","title":["eFPGA IP向け論理セルを対象としたテクノロジマッピングの提案と評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-08-21"},"_buckets":{"deposit":"c6b4b9b7-1e1f-4362-8e7f-e48eaaebdd92"},"_deposit":{"id":"238269","pid":{"type":"depid","value":"238269","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"eFPGA IP向け論理セルを対象としたテクノロジマッピングの提案と評価","author_link":["652470","652467","652469","652471","652468","652473","652466","652472"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"eFPGA IP向け論理セルを対象としたテクノロジマッピングの提案と評価"},{"subitem_title":"Preliminary proposal and evaluation of technology mapping for a logic cell architecture for eFPGA IP","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"回路設計","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2024-08-21","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"熊本大学半導体・デジタル研究教育機構"},{"subitem_text_value":"熊本大学大学院自然科学教育部"},{"subitem_text_value":"熊本大学大学院自然科学教育部"},{"subitem_text_value":"熊本大学半導体・デジタル研究教育機構"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/238269/files/IPSJ-DAS2024045.pdf","label":"IPSJ-DAS2024045.pdf"},"date":[{"dateType":"Available","dateValue":"2026-08-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2024045.pdf","filesize":[{"value":"1.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"af57f128-da94-4ead-8696-397fc6cd6e1d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"瀬戸, 謙修"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"岩崎, 凌大"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"佐々木, 龍也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯田, 全広"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kenshu, Seto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ryo, Iwasaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tatsuya, Sasaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masahiro, Iida","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"eFPGA IP 用に新規に提案された論理セルアーキテクチャは,LUT と比べて論理セル内の構成メモリを大幅に減らすことができ,複数出力を容易に取り出せる特徴を持つ.その新規論理セルの構成メモリ削減効果を実際の回路で確認するため,論理セル数を最小化するテクノロジマッピングを提案し,評価した.新規論理セルが 1 出力の場合,Yosys/ABC のテクノロジマッピングを活用する.ベンチマーク回路による評価の結果,新規論理セルが 1 出力の場合,LUT と比べて,構成メモリをほぼ半減できた.また,新規論理セルが複数出力を持つ場合に対応するため,グラフマッチングベースのプロトタイプ版テクノロジマッピングツールを開発した.","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The newly proposed logic cell architecture for eFPGA IP significantly reduces the configuration memory within the logic cell compared to LUTs and provides multiple outputs with little overhead. To demonstrate the reduction of the configuration memory by the new logic cell, a technology mapping that minimizes the number of the logic cells is proposed and evaluated. For single-output new logic cells, we propose a technology mapping utilizing existing logic synthesis tool Yosys/ABC. Evaluation using benchmark circuits confirmed that for single-output new logic cells, configuration memory is reduced by half compared to LUTs. For multi-output new logic cells, we developed a prototype technology mapping tool based on graph matching.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"291","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2024論文集"}],"bibliographicPageStart":"285","bibliographicIssueDates":{"bibliographicIssueDate":"2024-08-21","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2024"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":238269,"updated":"2025-01-19T08:37:06.994211+00:00","links":{},"created":"2025-01-19T01:41:23.793014+00:00"}