{"created":"2025-01-19T01:41:21.330593+00:00","updated":"2025-01-19T08:37:37.138062+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00238243","sets":["6164:6165:7651:11699"]},"path":["11699"],"owner":"44499","recid":"238243","title":["粗粒度再構成可能アーキテクチャにおけるマッピング結果の検証手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-08-21"},"_buckets":{"deposit":"b7ecb2cf-aaf6-4f49-adb1-4fc48c6ff97f"},"_deposit":{"id":"238243","pid":{"type":"depid","value":"238243","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"粗粒度再構成可能アーキテクチャにおけるマッピング結果の検証手法","author_link":["652312","652310","652307","652311","652308","652309"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"粗粒度再構成可能アーキテクチャにおけるマッピング結果の検証手法"},{"subitem_title":"A Verification Method of Mapping Result for CGRA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"設計支援","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2024-08-21","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"富士通株式会社"},{"subitem_text_value":"富士通株式会社"},{"subitem_text_value":"富士通株式会社"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Fujitsu Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu Ltd.","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/238243/files/IPSJ-DAS2024019.pdf","label":"IPSJ-DAS2024019.pdf"},"date":[{"dateType":"Available","dateValue":"2026-08-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2024019.pdf","filesize":[{"value":"1.6 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"f8cbf3ff-753a-48e2-8e00-9f3c3bb7f390","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"清水, 智弘"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"渡部, 康弘"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉川, 隆英"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Toshihiro, Shimizu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yasuhiro, Watanabe","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takahide, Yoshikawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"粗粒度再構成可能アーキテクチャ (CGRA) はエネルギー効率や計算性能に優れたハードウェアであり，近年アクセラレータ基盤として注目されている．CGRA ではデータフローグラフ (DFG) を演算器 (PE) 配列にマップする．そして性能改善等のためにマッピング結果を手動で最適化したり，自動最適化の研究開発をしたりするケースにおいて，最適化後でも期待通りの結果を導出できていることの検証が必須となる．しかし，この検証は PE のデータ通過に関する設定などのマッピング情報では不十分であり，全体のフローの情報が必須となる．本研究では CGRA におけるマッピング結果と DFG の等価性の検証方法を提案する．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Coarse-Grained Reconfigurable Architecture (CGRA) is a hardware which can achieve energy efficiency and high performance. CGRA has recently attracted attention as an accelerator platform. In CGRA, a data flow graph (DFG) is mapped to a processing element (PE) array. In the case of manual optimization of mapping for performance improvement or research and development of automatic optimization, it is required to verify that the computation with the mapping result is same with the DFG. However, for this verification, mapping information such as the setting on the data passage of PE is not sufficient, and the information of the whole flow is indispensable. In this paper, we propose a method to verify the mapping result in CGRA.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"127","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2024論文集"}],"bibliographicPageStart":"121","bibliographicIssueDates":{"bibliographicIssueDate":"2024-08-21","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2024"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":238243,"links":{}}