{"id":238229,"links":{},"created":"2025-01-19T01:41:19.978260+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00238229","sets":["6164:6165:7651:11699"]},"path":["11699"],"owner":"44499","recid":"238229","title":["貪欲法を用いた表面符号向けエラー訂正復号器のFPGA・ASIC実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-08-21"},"_buckets":{"deposit":"a442a233-b88e-459c-a9ca-cb52859116f5"},"_deposit":{"id":"238229","pid":{"type":"depid","value":"238229","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"貪欲法を用いた表面符号向けエラー訂正復号器のFPGA・ASIC実装","author_link":["652216","652215","652214","652218","652213","652217"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"貪欲法を用いた表面符号向けエラー訂正復号器のFPGA・ASIC実装"},{"subitem_title":"FPGA and ASIC Implementations of a Surface Code Error Correction Decoder Using a Greedy Algorithm","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"量子コンピュータ","subitem_subject_scheme":"Other"}]},"item_type_id":"18","publish_date":"2024-08-21","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_18_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"京都工芸繊維大学"},{"subitem_text_value":"東京大学"},{"subitem_text_value":"京都工芸繊維大学"}]},"item_18_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kyoto Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Kyoto Institute of Technology","subitem_text_language":"en"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/238229/files/IPSJ-DAS2024005.pdf","label":"IPSJ-DAS2024005.pdf"},"date":[{"dateType":"Available","dateValue":"2026-08-21"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-DAS2024005.pdf","filesize":[{"value":"987.4 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"d26c0b07-9cb1-4cf6-b89c-2a6afc2058b9","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Information Processing Society of Japan"}]},"item_18_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"青山, 連"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"門本, 淳一郎"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小林, 和淑"}],"nameIdentifiers":[{}]}]},"item_18_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Ren, Aoyama","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Junichiro, Kadomoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazutoshi, Kobayashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_18_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"実用的な計算をできる量子コンピュータの実現には誤り訂正機能が必要である．表面符号は代表的な誤り訂正手法のひとつであり高い誤り訂正機能を持つ．本研究では誤り訂正機能の一部である復号器をハードウェア記述言語である Verilog HDL を用いて設計した．設計にあたって，貪欲法と呼ばれるアルゴリズムを使用した．設計した FPGA を対象としたものと ASIC を対象としたものの 2 種類の復号器を 180nm プロセス，22nm プロセスを用いて論理合成を行った．FPGA を対象とした合成では使用リソースとして LUT と FF，ASIC 向けの合成では面積と消費電力を求めた．この結果を同様に反復貪欲法を用いた先行研究と比較した．比較の結果，FPGA 対象の合成において LUT は 229%，FF は 19% となり，ASIC 対象の合成において面積は 0.872%，消費電力は 2.96% となった．","subitem_description_type":"Other"}]},"item_18_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Error correction is mandatory to realize a quantum computer that can perform practical calculations. Surface codes are one of the error correction methods and have high error correction capability. In this study, we designed a decoder, which is a part of the error correction function, using Verilog HDL. An algorithm called the greedy method was used in the design. The decoder was synthesized using 180-nm process and a 22-nm cell libraries. Two types of synthesis were performed, one for FPGAs and the other for ASICs: LUTs and FFs were used as resources for synthesis for FPGAs, and area and power consumption were obtained for synthesis for ASICs. The results were compared with those of previous studies that also used the greedy method. The results showed that the LUT and FF used 229% and 19% of the resources for FPGA synthesis, respectively, while the area and power consumption for ASIC synthesis were 0.872% and 2.96%, respectively.","subitem_description_type":"Other"}]},"item_18_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"26","bibliographic_titles":[{"bibliographic_title":"DAシンポジウム2024論文集"}],"bibliographicPageStart":"22","bibliographicIssueDates":{"bibliographicIssueDate":"2024-08-21","bibliographicIssueDateType":"Issued"},"bibliographicVolumeNumber":"2024"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"updated":"2025-01-19T08:37:53.029180+00:00"}