{"id":237608,"updated":"2025-01-19T08:49:39.488649+00:00","links":{},"created":"2025-01-19T01:40:19.958997+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00237608","sets":["1164:1579:11464:11703"]},"path":["11703"],"owner":"44499","recid":"237608","title":["楽観/悲観構造的記号シミュレーションを用いたテスト並列化のためのドントケア割当て及びテストスケジューリング法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-08-01"},"_buckets":{"deposit":"589bf3dd-587c-41b8-af8d-c958fd55567c"},"_deposit":{"id":"237608","pid":{"type":"depid","value":"237608","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"楽観/悲観構造的記号シミュレーションを用いたテスト並列化のためのドントケア割当て及びテストスケジューリング法","author_link":["650731","650735","650733","650734","650729","650736","650730","650732"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"楽観/悲観構造的記号シミュレーションを用いたテスト並列化のためのドントケア割当て及びテストスケジューリング法"},{"subitem_title":"X-Filling and Test Scheduling Methods for Concurrent Testing Using Optimistcally/Pessmistically Strucural Symbolic Simulation","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"コンパイラ・最適化","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2024-08-01","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"日本大学大学院生産工学研究科"},{"subitem_text_value":"日本大学生産工学部"},{"subitem_text_value":"京都産業大学情報理工学部"},{"subitem_text_value":"日本大学生産工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Industrial Technology, Nihon University","subitem_text_language":"en"},{"subitem_text_value":"College of Industrial Technology, Nihon University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Information Science and Engineering, Kyoto Sangyo University","subitem_text_language":"en"},{"subitem_text_value":"College of Industrial Technology, Nihon University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/237608/files/IPSJ-ARC24258014.pdf","label":"IPSJ-ARC24258014.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC24258014.pdf","filesize":[{"value":"1.6 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"2a175380-4503-47fb-ae76-8cc1afe0596d","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"徳田, 晴太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"細川, 利典"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉村, 正義"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"新井, 雅之"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Haruta, Tokuta","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Toshinori, Hosokawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masayoshi, Yoshimura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masanori, Arai","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年，VLSI のテストコスト増大に伴い，テストパターン数の削減が重要になっている．テストパターン数を削減するためのレジスタ転送レベルでのテスト容易化設計手法が提案されている．その手法はデータパスの中のハードウェア要素を並列にテストすることを目的として，コントローラの状態遷移時にデータパスに供給される制御信号中のドントケア値に，論理値を割当てる．従来手法は，できる限り少数の状態遷移を用いて，できる限り多数のハードウェア要素をテストすることでテストパターン数の削減を図っている．本論文では，多数のテストパターンを必要とするハードウェア要素である演算器に着目し，できる限り多数の状態遷移で演算器を並列テストするようなドントケア割当て手法を提案し，さらにデータパスの推定テストパターン数を最小化するために，各状態遷移で生成するテストパターン数を決定するテストスケジューリング手法を提案する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In recent years, with the increasing test cost of VLSIs, it has become important to reduce the number of test patterns. Design-for-testability methods at register transfer level have been proposed to reduce the number of test patterns. The methods aim to concurrently test hardware elements in a data-path by assigning logical values to don't-care values (Xs) in control signals supplied to the data-path when a controller transitions between states. The conventional method aims to reduce the number of test patterns by testing as many hardware elements as possible using as few state transitions as possible. In this paper, we focus on operational units, which are hardware elements that require a large number of test patterns, and propose a X-filling method that concurrently tests operational units with as many state transitions as possible. We also propose a test scheduling method that determines the number of test patterns to be generated at each state transition in order to minimize the estimated number of test patterns for data-paths from controllers with X-filling.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2024-08-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"14","bibliographicVolumeNumber":"2024-ARC-258"}]},"relation_version_is_last":true,"weko_creator_id":"44499"}}