{"links":{},"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00237604","sets":["1164:1579:11464:11703"]},"path":["11703"],"owner":"44499","recid":"237604","title":["RIKEN CGRAにおける不均衡なデータフローの性能への影響の考察"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-08-01"},"_buckets":{"deposit":"e7035511-6b41-40de-a416-eb982acbcae1"},"_deposit":{"id":"237604","pid":{"type":"depid","value":"237604","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"RIKEN CGRAにおける不均衡なデータフローの性能への影響の考察","author_link":["650711","650710","650713","650708","650712","650714","650707","650709"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"RIKEN CGRAにおける不均衡なデータフローの性能への影響の考察"},{"subitem_title":"A study of the impact of imbalanced data flows on the RIKEN CGRA","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"ハードウェア設計・デバイス技術","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2024-08-01","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"理化学研究所計算科学研究センター プロセッサ研究チーム/明治大学理工学部情報科学科"},{"subitem_text_value":"明治大学理工学部情報科学科"},{"subitem_text_value":"理化学研究所計算科学研究センター プロセッサ研究チーム"},{"subitem_text_value":"理化学研究所計算科学研究センター プロセッサ研究チーム"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Processor Research Team, RIKEN R-CCS / Dept. of Computer Science, School of Sci.&Tech., Meiji University.","subitem_text_language":"en"},{"subitem_text_value":"Dept. of Computer Science, School of Sci.&Tech., Meiji University.","subitem_text_language":"en"},{"subitem_text_value":"Processor Research Team, RIKEN R-CCS","subitem_text_language":"en"},{"subitem_text_value":"Processor Research Team, RIKEN R-CCS","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/237604/files/IPSJ-ARC24258010.pdf","label":"IPSJ-ARC24258010.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC24258010.pdf","filesize":[{"value":"1.0 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"1f802ef0-1e7e-4d40-bf13-671635aa2faa","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"相原, 寧仁"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"宮島, 敬明"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Boma, Adhi"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"佐野, 健太郎"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yasuto, Aihara","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takaaki, Miyajima","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Boma, Adhi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kentaro, Sano","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"粗粒度再構成可能アーキテクチャ (CGRA) は,隣接する計算要素 (PE) を相互に接続した 2 次元アレイの構造を持つ.アプリケーションの実行に際し,計算をデータフローグラフに変換し,それを各 PE に配置してパイプライン化されたデータパスを構成する.実行時は,各 PE が必要なデータが到着し次第,演算を行うデータフローマシンとして動作する.データ到着のタイミングが大幅に異なるデータフローグラフ (DFG) では待ち合わせが発生し, PE の演算が間欠的に行われることで,計算スループットが低下してしまう.本研究では,PE の持つ FIFO キューを用いたタイミング調整方法において,FIFO 深さが計算スループットや回路面積に与える影響を考察する.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"2","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ(ARC)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2024-08-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"10","bibliographicVolumeNumber":"2024-ARC-258"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:40:19.573235+00:00","updated":"2025-01-19T08:49:44.562734+00:00","id":237604}