{"updated":"2025-01-22T20:16:13.827204+00:00","links":{},"id":23693,"created":"2025-01-18T22:55:01.959986+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00023693","sets":["1164:1579:1628:1630"]},"path":["1630"],"owner":"1","recid":"23693","title":["MIPSベースマルチスレッドプロセッサのFPGAによる実装と評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2000-08-03"},"_buckets":{"deposit":"711ea8cf-549f-492a-93bf-6cb8fd16156d"},"_deposit":{"id":"23693","pid":{"type":"depid","value":"23693","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"MIPSベースマルチスレッドプロセッサのFPGAによる実装と評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"MIPSベースマルチスレッドプロセッサのFPGAによる実装と評価"},{"subitem_title":"Implementation and Evaluation of a Multi - Threading Processor Based on MIPS Architecture by Using FPGA","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2000-08-03","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"電子技術総合研究所情報アーキテクチャ部"},{"subitem_text_value":"電子技術総合研究所情報アーキテクチャ部"},{"subitem_text_value":"電子技術総合研究所情報アーキテクチャ部／電機通信大学大学院情報システム学研究科"},{"subitem_text_value":"電子技術総合研究所情報アーキテクチャ部／筑波大学電子・情報工学系"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Computer Science Division, Electrotechnical Laboratory","subitem_text_language":"en"},{"subitem_text_value":"Computer Science Division, Electrotechnical Laboratory","subitem_text_language":"en"},{"subitem_text_value":"Computer Science Division, Electrotechnical Laboratory/Graduate School of Information Systems, The University of Electro - Communications","subitem_text_language":"en"},{"subitem_text_value":"Computer Science Division, Electrotechnical Laboratory/Institute of Information Scicnces and Electronics, University of Tsukuba","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/23693/files/IPSJ-ARC00139026.pdf"},"date":[{"dateType":"Available","dateValue":"2002-08-03"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC00139026.pdf","filesize":[{"value":"561.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"9a8bf7a6-953b-40cf-91d2-1e8c88929767","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2000 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"佐谷野, 健二"},{"creatorName":"児玉, 祐悦"},{"creatorName":"坂根, 広史"},{"creatorName":"山口, 喜教"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kenji, Sayano","creatorNameLang":"en"},{"creatorName":"Yuetsu, Kodama","creatorNameLang":"en"},{"creatorName":"Hirofumi, Sakane","creatorNameLang":"en"},{"creatorName":"Yoshinori, Yamaguchi","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本研究では，FPGA上にMIPSアーキテクチャをベースとしたプロセッサコアの実装を行い，このプロセッサコアにEM-Xのマルチスレッド処理メカニズムを試験的に導入した．一般に広く使用されているMIPSアーキテクチャにEM-Xのマルチスレッド処理メカニズムを導入することで，これらのメカニズムの有用性を検証するとともに，パイプライン段数の増加による高周波数動作に対応したプロセッサの開発を目指す．またEM-Xのネットワークルータに対しても高周波数動作に対応する為の変更を行い，プロセッサ全体の性能のバランスを考慮して改良を行った．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this research we developed a MIPS based processor by using FPGA in which the multi-threading mechanisms of EM-X wate introduced experimentally. The goal of this research is to prove the efficiency of the mechanisms and to enhance the multi-threading processor architecture with long pipeline approach, by introducing the multi-threading mechanisms of EM-X into ordinary MIPS architecture. Also, the network router was enhanced to operate on higher frequency to keep the performance balance of network and processor.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"156","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"151","bibliographicIssueDates":{"bibliographicIssueDate":"2000-08-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"74(2000-ARC-139)","bibliographicVolumeNumber":"2000"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}