{"created":"2025-01-18T22:55:01.069013+00:00","updated":"2025-01-22T20:15:35.565056+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00023673","sets":["1164:1579:1628:1630"]},"path":["1630"],"owner":"1","recid":"23673","title":["シリーズパラレル型レジスタ生存グラフを用いたレジスタ割付けへの動的計画法の適用"],"pubdate":{"attribute_name":"公開日","attribute_value":"2000-08-03"},"_buckets":{"deposit":"71b4f575-4ee5-4ba6-91e8-cc1971da9f1e"},"_deposit":{"id":"23673","pid":{"type":"depid","value":"23673","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"シリーズパラレル型レジスタ生存グラフを用いたレジスタ割付けへの動的計画法の適用","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"シリーズパラレル型レジスタ生存グラフを用いたレジスタ割付けへの動的計画法の適用"},{"subitem_title":"Applying Dynamic Programming Technique to Register Allocation Based on Series - parallelized Register Existence Graph","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2000-08-03","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"早稲田大学理工学部"},{"subitem_text_value":"（株）東芝研究開発センター"},{"subitem_text_value":"日本IBM（株）東京基礎研究所"},{"subitem_text_value":"日本IBM（株）東京基礎研究所"},{"subitem_text_value":"早稲田大学理工学部"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"School of Science and Engineering, Waseda Univ.","subitem_text_language":"en"},{"subitem_text_value":"Tohshiba Corp. Corporate Research and Development Center","subitem_text_language":"en"},{"subitem_text_value":"Tokyo Research Laboratory, IBM Japan, Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Tokyo Research Laboratory, IBM Japan, Ltd.","subitem_text_language":"en"},{"subitem_text_value":"School of Science and Engineering, Waseda Univ.","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/23673/files/IPSJ-ARC00139006.pdf"},"date":[{"dateType":"Available","dateValue":"2002-08-03"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC00139006.pdf","filesize":[{"value":"650.9 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"7046afbd-7c60-4190-aba1-c351821ddb01","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2000 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"淺原, 英雄"},{"creatorName":"近藤, 伸宏"},{"creatorName":"古関, 聰"},{"creatorName":"小松, 秀昭"},{"creatorName":"深澤, 良彰"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Hideo, Asahara","creatorNameLang":"en"},{"creatorName":"Nobuhiro, Kondoh","creatorNameLang":"en"},{"creatorName":"Akira, Koseki","creatorNameLang":"en"},{"creatorName":"Hideaki, Komatsu","creatorNameLang":"en"},{"creatorName":"Yoshiaki, Fukazawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本稿では、命令レベル並列プロセッサ向けの新しいレジスタ割付け手法を提案する。命令レベル並列性(ILP)を抽出する手法として、我々はシリーズパラレル型レジスタ生存グラフを用いた手法を提案してきた。しかし、今までの手法はワンパスのヒューリスティクスを用いた手法であったため、プログラム構造によってはオプティマムな解を得ることができないという欠点があった。そこで、解空間を広く探索し、かつ、動的計画法を用いて計算量が増加するのを抑制できるアルゴリズムを開発した。本稿では、まずレジスタ割付けに関する問題を整理し、本手法のアルゴリズムと適用例を示し、その評価を行う。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"We introduce a new register allocation algorithm for instruction-level parallelism processors. We have suggested a method using Series-Parallelized Register Existence Graph in order to extract ILP in a program. However, this method does not always give the optimum result because it only uses one-pass heuristics. Then, we developed a new algorithm which can search the broader possibility of solutions and uses dynamic programming in order to reduce the cost of computation. In this paper, we clarify some problems on register allocation techniques, and give our algorithm with some examples, and its evaluation.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"36","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"31","bibliographicIssueDates":{"bibliographicIssueDate":"2000-08-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"74(2000-ARC-139)","bibliographicVolumeNumber":"2000"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":23673,"links":{}}