{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00023575","sets":["1164:1579:1622:1624"]},"path":["1624"],"owner":"1","recid":"23575","title":["大容量FPGA の応用によるマルチプロセッサエミュレーションシステムの評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2001-07-25"},"_buckets":{"deposit":"360e2fe2-d6ea-4122-803e-ee9deeb4c42b"},"_deposit":{"id":"23575","pid":{"type":"depid","value":"23575","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"大容量FPGA の応用によるマルチプロセッサエミュレーションシステムの評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"大容量FPGA の応用によるマルチプロセッサエミュレーションシステムの評価"},{"subitem_title":"Evaluation of a Multiprocessor Emulation System by the Application of Large - scale FPGA","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2001-07-25","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"科学技術振興事業団科学技術特別研究員"},{"subitem_text_value":"産業技術総合研究所情報処理研究部門"},{"subitem_text_value":"産業技術総合研究所情報処理研究部門"},{"subitem_text_value":"産業技術総合研究所情報処理研究部門"},{"subitem_text_value":"産業技術総合研究所情報処理研究部門"},{"subitem_text_value":"株式会社創夢"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Domestic Research Fellow, Japan Science and Technology Corporation","subitem_text_language":"en"},{"subitem_text_value":"Information Technology Research Institute, National Institute of Advanced Industrial Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Information Technology Research Institute, National Institute of Advanced Industrial Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Information Technology Research Institute, National Institute of Advanced Industrial Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Information Technology Research Institute, National Institute of Advanced Industrial Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"SOUM Corporation","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/23575/files/IPSJ-ARC01144005.pdf"},"date":[{"dateType":"Available","dateValue":"2003-07-25"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC01144005.pdf","filesize":[{"value":"159.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"d00e5e70-0f74-494c-8b69-35680e8fcf82","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2001 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"佐谷野, 健二"},{"creatorName":"片下, 敏宏"},{"creatorName":"小池, 汎平"},{"creatorName":"児玉, 祐悦"},{"creatorName":"坂根, 広史"},{"creatorName":"甲村, 康人"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kenji, Sayano","creatorNameLang":"en"},{"creatorName":"Toshihiro, Katashita","creatorNameLang":"en"},{"creatorName":"Hanpei, Koike","creatorNameLang":"en"},{"creatorName":"Yuetsu, Kodama","creatorNameLang":"en"},{"creatorName":"Hirofumi, Sakane","creatorNameLang":"en"},{"creatorName":"Yasuhito, Koumura","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本研究では，大容量FPGA を応用したマルチプロセッサ向けエミュレーションシステムの開発を行った．本システムでは，プロセッサとネットワークルータを単一のFPGA チップ上に実装することで，高速なエミュレーション動作と高い柔軟性を実現している．また，独立した複数のメモリバスにより多様な構造のPE に対応し，高速な差動信号バスを用いることによりシステム全体の性能を考慮して設計が行われている．本稿では，エミュレーションシステムを構成する各コンポーネントの評価結果について述べる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In this research, we developed a multiprocessor emulation system by the application of large-scale FPGA. This system realizes very high-speed emulation and high flexibility, since processors and network routers are implemented in a single FPGA chip. Furthermore, various PE structures can be implemented with the individual memory buses, and the system performance at multiprocessor emulation is enhanced with the high-speed differential I/O buses. In this paper, we describe the evaluation results on each component of the emulation system.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"30","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"25","bibliographicIssueDates":{"bibliographicIssueDate":"2001-07-25","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"76(2001-ARC-144)","bibliographicVolumeNumber":"2001"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":23575,"updated":"2025-01-22T20:18:27.286706+00:00","links":{},"created":"2025-01-18T22:54:56.783875+00:00"}