{"id":23493,"updated":"2025-01-22T20:22:26.007837+00:00","links":{},"created":"2025-01-18T22:54:53.148521+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00023493","sets":["1164:1579:1616:1618"]},"path":["1618"],"owner":"1","recid":"23493","title":["共有変数の同期を考慮したキャッシュ構成とその予備実験"],"pubdate":{"attribute_name":"公開日","attribute_value":"2002-08-22"},"_buckets":{"deposit":"be40b376-0784-44bf-8955-ae2266836cf8"},"_deposit":{"id":"23493","pid":{"type":"depid","value":"23493","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"共有変数の同期を考慮したキャッシュ構成とその予備実験","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"共有変数の同期を考慮したキャッシュ構成とその予備実験"},{"subitem_title":"Organization and Preliminary Experiment for Cache Considering Synchronization of Shared Variable","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2002-08-22","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州工業大学工学部電気工学科"},{"subitem_text_value":"九州工業大学工学部電気工学科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Depertment of Electronic Engineering, Faculty of Engineering, Kyushu Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"Depertment of Electronic Engineering, Faculty of Engineering, Kyushu Institute of Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/23493/files/IPSJ-ARC02149023.pdf"},"date":[{"dateType":"Available","dateValue":"2004-08-22"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC02149023.pdf","filesize":[{"value":"193.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"2d763569-d0ce-41fb-a8bf-b5ea7c28aa75","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2002 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山脇, 彰"},{"creatorName":"岩根, 雅彦"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Akira, Yamawaki","creatorNameLang":"en"},{"creatorName":"Masahiko, Iwane","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"共有メモリ型マルチプロセッサにおけるマルチスレッド実行環境では，複数のスレッドが共有変数を介して通信と同期を行う．TSVMは共有変数へのアクセスと同時に同期を行う論理的な構造化メモリである．物理TSVMはマルチプロセッサオンチップ(MOC)において，TSVMキャッシュ(TC)と通常のメモリによって実現される．CPUコアのL1キャッシュは，データキャッシュをTCと一般変数キャッシュ(GVC)に分離したキャッシュアーキテクチャである．基礎実験として，スタンドアロンのTSVMを搭載した実機での実測結果からTCによって性能向上が見込まれた．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"In a multithreaded environment, an inter-thread communication and a synchronization are performed through a shared variable in a shared memory. TSVM is a structured memory with synchronization that performs an inter-thread comminucation and a synchronization simultaneously. In Multiprocessor-On-a-Chip(MOC),  the physical TSVM consists of TSVM Cache(TC) and a conventional memory. CPU core has L1 cache including TC, General Variable Cache(GVC), and instruction cache. This cache architecture is the one that devides a conventional data cache into TC and GVC. As preliminary experiment, we estimate performance of TC using the measurement data on MTA/TSVM with the stand-alone TSVM. The estimation shows that TC achieves a good performance.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"138","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"133","bibliographicIssueDates":{"bibliographicIssueDate":"2002-08-22","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"81(2002-ARC-149)","bibliographicVolumeNumber":"2002"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}