{"updated":"2025-01-19T09:45:56.554325+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00234573","sets":["1164:1579:11464:11617"]},"path":["11617"],"owner":"44499","recid":"234573","title":["ニューラルネットワーク計算のためのメモリ中心型可変並列性CGRAの検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-06-03"},"_buckets":{"deposit":"837e8e05-3d9a-40f8-b5ad-e55a95ca8eee"},"_deposit":{"id":"234573","pid":{"type":"depid","value":"234573","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"ニューラルネットワーク計算のためのメモリ中心型可変並列性CGRAの検討","author_link":["639358","639355","639353","639360","639356","639357","639354","639359"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ニューラルネットワーク計算のためのメモリ中心型可変並列性CGRAの検討"},{"subitem_title":"Memory-centric CGRA with variable parallelism for neural networks","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"メモリ管理・活用","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2024-06-03","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"北海道大学大学院情報科学院"},{"subitem_text_value":"北海道大学大学院情報科学研究院"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Technology, Hokkaido University","subitem_text_language":"en"},{"subitem_text_value":"Faculty of Information Science and Technology, Hokkaido University ","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing 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symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年ニューラルネットワークモデルは大規模化，多様化しており様々なモデルを高速に処理できる専用演算器が求められている．本研究では複数のモデルに対して最適な並列性，計算順序を選択可能な可変並列性アーキテクチャを検討する．本研究の基本的なアーキテクチャは積和演算ユニット PE とそれに付属するメモリを並べたものであり，メモリや PE の接続及びデータフローを変化させることで可変並列性を実現する CGRA アーキテクチャである．全結合層において選択可能な 5 通りの計算手順とそれに対応する接続を示した．各計算手順での演算にかかるサイクル数とデータレートを評価し，これにより要求に応じて計算手順を選択する方法を示した．さらに，必要となるメモリの物理的なサイズについて概算した．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ（ARC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2024-06-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"29","bibliographicVolumeNumber":"2024-ARC-257"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:36:22.457397+00:00","id":234573,"links":{}}