{"updated":"2025-01-22T20:25:02.977414+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00023376","sets":["1164:1579:1610:1612"]},"path":["1612"],"owner":"1","recid":"23376","title":["リザーベーションステーションと物理レジスタ・ファイルを併用するスーパースケーラ・プロセッサ"],"pubdate":{"attribute_name":"公開日","attribute_value":"2003-08-05"},"_buckets":{"deposit":"a44e6d1a-c2ef-4fd1-a8af-8220e697c1f1"},"_deposit":{"id":"23376","pid":{"type":"depid","value":"23376","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"リザーベーションステーションと物理レジスタ・ファイルを併用するスーパースケーラ・プロセッサ","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"リザーベーションステーションと物理レジスタ・ファイルを併用するスーパースケーラ・プロセッサ"},{"subitem_title":"A Superscalar Processor Using Reservation Station and Physical Register File Together","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2003-08-05","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"京都大学"},{"subitem_text_value":"京都大学"},{"subitem_text_value":"京都大学"},{"subitem_text_value":"京都大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Kyoto University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/23376/files/IPSJ-ARC03154003.pdf"},"date":[{"dateType":"Available","dateValue":"2005-08-05"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC03154003.pdf","filesize":[{"value":"524.4 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"101d1a58-14f5-4a8a-a092-648f775a659c","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2003 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"小西, 将人"},{"creatorName":"五島, 正裕"},{"creatorName":"森, 眞一郎"},{"creatorName":"富田, 眞治"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masahito, Konishi","creatorNameLang":"en"},{"creatorName":"Masahiro, Goshima","creatorNameLang":"en"},{"creatorName":"Shin-Ichiro, Mori","creatorNameLang":"en"},{"creatorName":"Shinji, Tomita","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年では，命令が発行されてから実行されるまでのレイテンシ，発行レイテンシの増加と，小容量化に伴う1次キャッシュ・ミス率の悪化のため，投機的スケジューリング・ミスによる性能低下が問題となりつつある．本稿では，最近多くの高性能なプロセッサが採用している物理レジスタ・ファイルを用いたout-of-order実行方式に対して，リザーベーション・ステーションを併用する技術を提案する．この方式では，レジスタ読み出しをバックエンドではなく，フロントエンドで行うことにより，発行レイテンシを半減することができる．シミュレーションの結果，SPEC95ベンチマークでは平均で20.0%の性能向上を確認した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Recently, the increase of issue latency is becoming a problem.  Issue latency is cycles from the instruction scheduling to actual execution. The increase of the issue latency increases miss-penalty of instruction scheduling and degrades the performance. When a line buffer is used to reduce load latency, scheduling misses will occurs with high frequency and the issue latency problem will become apparent.  This paper introduces yet another design of a superscalar processor using a reservation station and a physical register file together. Since the register file read is performed in the front-end, it can drastically reduce the issue latency.  Evaluation result shows it achieves an average speed-up of 20% for the SPEC95 benchmark.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"18","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"13","bibliographicIssueDates":{"bibliographicIssueDate":"2003-08-05","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"84(2003-ARC-154)","bibliographicVolumeNumber":"2003"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:54:47.968539+00:00","id":23376,"links":{}}