{"updated":"2025-01-19T10:00:46.163634+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00233716","sets":["934:1119:11590:11591"]},"path":["11591"],"owner":"44499","recid":"233716","title":["極低温不揮発FPGAを対象とした誤り耐性量子コンピュータ向け表面符号復号器のRTL設計"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-03-26"},"_buckets":{"deposit":"f6ac40af-2d65-4490-b2df-c7a5f259ea38"},"_deposit":{"id":"233716","pid":{"type":"depid","value":"233716","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"極低温不揮発FPGAを対象とした誤り耐性量子コンピュータ向け表面符号復号器のRTL設計","author_link":["635442","635449","635445","635447","635448","635450","635446","635454","635444","635451","635441","635443","635453","635452"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"極低温不揮発FPGAを対象とした誤り耐性量子コンピュータ向け表面符号復号器のRTL設計"},{"subitem_title":"RTL Design of Surface Code Decoder for Fault-Tolerant Quantum Computers Targeting Cryogenic Non-volatile FPGAs","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"量子コンピュータ，量子誤り訂正，表面符号，不揮発FPGA，RTL設計","subitem_subject_scheme":"Other"}]},"item_type_id":"3","publish_date":"2024-03-26","item_3_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"九州大学"},{"subitem_text_value":"ナノブリッジ・セミコンダクター株式会社"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"九州大学"},{"subitem_text_value":"ナノブリッジ・セミコンダクター株式会社"},{"subitem_text_value":"ナノブリッジ・セミコンダクター株式会社"},{"subitem_text_value":"九州大学"}]},"item_3_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"NanoBridge Semiconductor, Inc.","subitem_text_language":"en"},{"subitem_text_value":"Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"Kyushu University","subitem_text_language":"en"},{"subitem_text_value":"NanoBridge Semiconductor, Inc.","subitem_text_language":"en"},{"subitem_text_value":"NanoBridge Semiconductor, Inc.","subitem_text_language":"en"},{"subitem_text_value":"Kyushu University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/233716/files/IPSJ-TACS1701003.pdf","label":"IPSJ-TACS1701003.pdf"},"date":[{"dateType":"Available","dateValue":"2026-03-26"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-TACS1701003.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"11"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"15"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"72df9865-a916-4044-aa75-206799821e64","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Information Processing Society of Japan"}]},"item_3_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"中村, 徹舟"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"宮村, 信"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"井上, 弘士"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"川上, 哲志"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"阪本, 利司"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"多田, 宗弘"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"谷本, 輝夫"}],"nameIdentifiers":[{}]}]},"item_3_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tesshu, Nakamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Makoto, Miyamura","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Koji, Inoue","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Satoshi, Kawakami","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Toshitugu, Sakamoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Munehiro, Tada","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Teruo, Tanimoto","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_3_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11833852","subitem_source_identifier_type":"NCID"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_6501","resourcetype":"journal article"}]},"item_3_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1882-7829","subitem_source_identifier_type":"ISSN"}]},"item_3_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"量子ハードウェアは高いエラー率を示すため，量子誤り訂正技術の実現が不可欠である．特に，表面符号は高いエラー訂正性能を持つ誤り訂正符号として注目されている．本研究では，極低温環境で動作可能なNanoBridge-FPGAへの実装を目指し，iterative greedyアルゴリズムを用いた表面符号復号器のRTL設計を行った．設計した復号器は，先行研究と同じ誤りシミュレータを用いて動作検証を行い，レイテンシ・使用リソース量の評価も行った．さらに，NanoBridge-FPGAへの論理合成・配置配線も行い，使用リソース量を確認した．","subitem_description_type":"Other"}]},"item_3_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Since the error rates of existing quantum devices are high, it is essential to realize quantum error correction (QEC) techniques. In particular, surface code (SC) has attracted attention as one of the most promising error-correcting codes. In this study, we have designed an RTL surface code decoder using the iterative greedy algorithm to implement on NanoBridge-FPGA that can operate in cryogenic environments. The designed decoder was verified using the same error simulator as in the previous study, and latency and resource usage were also evaluated. In addition, we performed logic synthesis, placement and routing targeting NanoBridge-FPGA and confirmed the resource usage.","subitem_description_type":"Other"}]},"item_3_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"25","bibliographic_titles":[{"bibliographic_title":"情報処理学会論文誌コンピューティングシステム（ACS）"}],"bibliographicPageStart":"13","bibliographicIssueDates":{"bibliographicIssueDate":"2024-03-26","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"17"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:35:15.469076+00:00","id":233716,"links":{}}