{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00023367","sets":["1164:1579:1610:1611"]},"path":["1611"],"owner":"1","recid":"23367","title":["サーバ用CPUのハードウェア資源削減に基づくチップマルチプロセッサの設計"],"pubdate":{"attribute_name":"公開日","attribute_value":"2003-11-27"},"_buckets":{"deposit":"6725de7f-e76d-4b5b-b49a-07ccb39484c5"},"_deposit":{"id":"23367","pid":{"type":"depid","value":"23367","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"サーバ用CPUのハードウェア資源削減に基づくチップマルチプロセッサの設計","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"サーバ用CPUのハードウェア資源削減に基づくチップマルチプロセッサの設計"},{"subitem_title":"Designing High Throughput Chip Multiprocessor by Reducing Hardware Resources of Server Processor","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2003-11-27","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"（株）富士通研究所"},{"subitem_text_value":"（株）富士通研究所"},{"subitem_text_value":"（株）富士通研究所"},{"subitem_text_value":"（株）富士通研究所"},{"subitem_text_value":"富士通株式会社"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"FUJITSU LABORATORIES LTD.","subitem_text_language":"en"},{"subitem_text_value":"FUJITSU LABORATORIES LTD.","subitem_text_language":"en"},{"subitem_text_value":"FUJITSU LABORATORIES LTD.","subitem_text_language":"en"},{"subitem_text_value":"FUJITSU LABORATORIES LTD.","subitem_text_language":"en"},{"subitem_text_value":"FUJITSU LIMITED","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/23367/files/IPSJ-ARC03155008.pdf"},"date":[{"dateType":"Available","dateValue":"2005-11-27"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC03155008.pdf","filesize":[{"value":"186.3 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"2e46713c-6095-4013-88cc-e72a109a1e59","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2003 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"河場, 基行"},{"creatorName":"大河原, 英喜"},{"creatorName":"安島, 雄一郎"},{"creatorName":"安里, 彰"},{"creatorName":"安藤寿茂"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Motoyuki, Kawaba","creatorNameLang":"en"},{"creatorName":"Hideki, Okawara","creatorNameLang":"en"},{"creatorName":"Yuichiro, Ajima","creatorNameLang":"en"},{"creatorName":"Akira, Asato","creatorNameLang":"en"},{"creatorName":"Hisashige, Ando","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"ビジネスアプリケーション分野で使用されるシステムは，単体スレッドの性能よりむしろスループット性能が要求される．この要件に答えるため我々は小型のプロセッサを複数搭載したCMPの検討を行っている．本論文は，既存のサーバプロセッサであるSPARC64 Vをベースした小型CPUコアの設計について述べたものである．SPARC64 Vのシミュレータや実チップデータを利用しながら，4ステップにわたる段階的なハードウェア削減を行った結果，コア面積で54.5%，性能で70.9% 程度を達成するCPUコアが実装できることがわかった．またこのコアを用いた2コアCMPによりほぼ同一チップ面積で22% のスループット向上が得られることを確認した．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"The commercial workloads requires total throughput rather than the performance for a single thread. To meet this situation, we have studied a CMP system with simple processors. This paper describes the design of the simple processor based on a server processor, SPARC64 V. Utilizing the system simulator of SPARC64 V and actual chip information, we have applied 4-staged reduction of CPU hardware resources carefully. The performance of our eventual processor core is 70.9% of SPARC64 V, while the core occupies only 54.5% area．The CMP system  with 2 CPU cores can  deliver 22% higher through-put than SPARC64 V.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"62","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"57","bibliographicIssueDates":{"bibliographicIssueDate":"2003-11-27","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"119(2003-ARC-155)","bibliographicVolumeNumber":"2003"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":23367,"updated":"2025-01-22T20:26:04.890379+00:00","links":{},"created":"2025-01-18T22:54:47.571830+00:00"}