{"id":233496,"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00233496","sets":["1164:2822:11469:11529"]},"path":["11529"],"owner":"44499","recid":"233496","title":["マルチコアRISC-Vプロセッサ用コンテキストキャッシュの設計"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-03-14"},"_buckets":{"deposit":"c9b58e32-ceb3-4d03-9f03-d72896a757b3"},"_deposit":{"id":"233496","pid":{"type":"depid","value":"233496","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"マルチコアRISC-Vプロセッサ用コンテキストキャッシュの設計","author_link":["634346","634348","634352","634349","634350","634351","634353","634347"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチコアRISC-Vプロセッサ用コンテキストキャッシュの設計"},{"subitem_title":"Context Cache Design for Multicore RISC-V Processors","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"プロセッサ・アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2024-03-14","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":" 慶應義塾大学理工学部"},{"subitem_text_value":"株式会社アクセル"},{"subitem_text_value":"株式会社アクセル"},{"subitem_text_value":"慶應義塾大学理工学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Axell Corporation","subitem_text_language":"en"},{"subitem_text_value":"Axell Corporation","subitem_text_language":"en"},{"subitem_text_value":"Guraduate School of Science and Technology, Keio University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/233496/files/IPSJ-EMB24065019.pdf","label":"IPSJ-EMB24065019.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-EMB24065019.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"42"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"4bacad0e-e47c-47f8-860f-660e615924b1","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山澤, 彪"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"伊藤, 務"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"水頭, 一壽"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山﨑, 信行"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Akira, Yamazawa","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tsutomu, Itou","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kazutoshi, Suito","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Nobuyuki, Yamasaki","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12149313","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-868X","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"昨今，プログラムは複数のスレッドを用いて処理が実行される場合が多い．スレッドを複数用いて実行する場合，プロセッサ上で実行するスレッドを交換する際にコンテキストスイッチが発生する．この処理には，一般的に数百クロックかかる．コンテキストスイッチが頻繁に発生するようなプログラムでは性能を低下させる要因となる．コンテキストスイッチのオーバヘッドはオンチップの専用キャッシュであるコンテキストキャッシュを用いることで削減することができる．本研究ではマルチコア RISC-V プロセッサ用のコンテキストキャッシュを設計し，擬似的なスレッドの同時実行を行った．そして，コンテキストキャッシュの有効性をプログラムで評価したところ，提案手法によってコンテキストスイッチのオーバヘッドを削減することができた．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Today, programs are executed using multiple threads. When multiple threads are used for execution, a context switch occurs when the threads are exchanged. The context switch saves the information necessary for the computation (context) to memory and retrieves the context of the next thread from memory. This process results in a large overhead. The context switch overhead can be reduced by using a on-chip cache, the context cache. In this study, we designed the context cache for multi-core RISC-V processors. The results were evaluated with and without the context cache. The proposed method reduces the overhead of context switches.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告組込みシステム（EMB）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2024-03-14","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"19","bibliographicVolumeNumber":"2024-EMB-65"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"updated":"2025-01-19T10:04:39.020824+00:00","created":"2025-01-19T01:34:58.539490+00:00","links":{}}