{"created":"2025-01-19T01:34:52.976420+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00233439","sets":["1164:2036:11466:11528"]},"path":["11528"],"owner":"44499","recid":"233439","title":["TSNでの利用に向けた低遅延DMAコントローラの実装"],"pubdate":{"attribute_name":"公開日","attribute_value":"2024-03-14"},"_buckets":{"deposit":"9040403f-fa6b-4f1e-b0e7-fc4f629ef27b"},"_deposit":{"id":"233439","pid":{"type":"depid","value":"233439","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"TSNでの利用に向けた低遅延DMAコントローラの実装","author_link":["634070","634071","634072"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"TSNでの利用に向けた低遅延DMAコントローラの実装"},{"subitem_title":"Implementation of Low-Latency DMA Controller for Time-Sensitive Networking","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アクセラレータ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2024-03-14","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"株式会社東芝研究開発センター"},{"subitem_text_value":"株式会社東芝研究開発センター"},{"subitem_text_value":"株式会社東芝研究開発センター"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Corporate Research & Development Center, Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Corporate Research & Development Center, Toshiba Corporation","subitem_text_language":"en"},{"subitem_text_value":"Corporate Research & Development Center, Toshiba Corporation","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/233439/files/IPSJ-SLDM24205008.pdf","label":"IPSJ-SLDM24205008.pdf"},"date":[{"dateType":"Available","dateValue":"2026-03-14"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM24205008.pdf","filesize":[{"value":"493.8 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"6de7931a-41b6-4442-85cd-f594772410e9","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2024 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"小林, 優太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"オゲ, ヤースィン"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山浦, 隆博"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"TSN（Time-Sensitive Networking）は，優先度の異なる複数のキューを用いることで一つの物理ネットワーク上で様々な特性の通信を共存しながら，低遅延通信を実現する．しかしながら，TSN が対象とする範囲はネットワークインタフェースカード（NIC）の通信処理部分のみであり，エンドツーエンドでの遅延を考えるとメインメモリと NIC 間のデータ受け渡しの低遅延性も必要となる．本論文では，TSN での利用を想定した DMA コントローラ（DMAC）を提案する．本提案の DMAC は，低優先度のデータ転送が高優先度データ転送に影響を与えないようにメモリ読み出しリクエストの発行タイミングを制御することで，メインメモリと NIC 間のデータ転送時間を低減する．実験により，本提案の DMAC と TSN 規格の一つである Frame Preemption（FPE）を組み合わせることで，エンドツーエンドの通信時間が 99 パーセンタイルにおいて約 30.5% 削減できることが確認された．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"10","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2024-03-14","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"8","bibliographicVolumeNumber":"2024-SLDM-205"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":233439,"updated":"2025-01-19T10:05:48.447868+00:00","links":{}}