{"created":"2025-01-18T22:54:43.199303+00:00","updated":"2025-01-22T20:29:14.810631+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00023268","sets":["1164:1579:1604:1605"]},"path":["1605"],"owner":"1","recid":"23268","title":["メモリ投機を支援するCMPキャッシュコヒーレンスプロトコルの検討"],"pubdate":{"attribute_name":"公開日","attribute_value":"2004-12-02"},"_buckets":{"deposit":"68b87f0c-ef06-4750-8f20-81063844e738"},"_deposit":{"id":"23268","pid":{"type":"depid","value":"23268","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"メモリ投機を支援するCMPキャッシュコヒーレンスプロトコルの検討","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"メモリ投機を支援するCMPキャッシュコヒーレンスプロトコルの検討"},{"subitem_title":"Cache Coherency Protocols for Memory Speculation on CMP","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2004-12-02","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院情報理工学系研究科"},{"subitem_text_value":"東京大学大学院情報理工学系研究科"},{"subitem_text_value":"東京大学大学院情報理工学系研究科／現在、日本テキサス・インスツルメンツ株式会社"},{"subitem_text_value":"東京大学大学院情報理工学系研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Information Science and Technology, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Technology, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Technology, The University of Tokyo/Presently with Texas Instruments Japan Ltd.","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Technology, The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/23268/files/IPSJ-ARC04160009.pdf"},"date":[{"dateType":"Available","dateValue":"2006-12-02"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC04160009.pdf","filesize":[{"value":"321.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"9e726c72-6cfc-4628-85d3-07cc0326ed12","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2004 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"豊島, 隆志"},{"creatorName":"田代, 大輔"},{"creatorName":"バルリニコデムス"},{"creatorName":"坂井, 修一"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takashi, Toyoshima","creatorNameLang":"en"},{"creatorName":"Daisuke, Tashiro","creatorNameLang":"en"},{"creatorName":"Niko, DemusBarli","creatorNameLang":"en"},{"creatorName":"Shuichi, Sakai","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"半導体プロセスの微細化に伴いチップマルチプロセッサが一般化しつつある。複数のプロセッサコアを有効活用する手法としてスレッド投機実行と呼ばれるマルチスレッド化手法が提案されてきた。スレッド投機の実現にはいくつかの付加的なハードウェアが必要となるが、本稿ではメモリ投機を支援する機構としてキャッシュコヒーレンスプロトコルに着目し、スレッド投機実行に起因するキャッシュミスを複数のプロトコルで評価した。その結果、ブロードキャストの適用により性能は約30%向上することがわかった。また、最も高い性能を達成したのは更新方式であるが、更新方式と無効化方式の性能差は6?9%程度であり、ブロードキャストの適用効果に比べ、設計の複雑な更新方式を採用するメリットは小さいことがわかった。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Chip Multiprocessors are becoming common with the decreases in size of device dimensions.Speculative Multithreading which effectively uses multiprocessors to improve performance of sequential programs has been proposed. However, additional hardwares are needed for realization of Speculative Multithreading. In this paper, we focus on cache coherency protocols as a mechanism to support memory speculation. We study cache misses caused by Speculative Multithreading on candidate protocols. As a result, we improve performance with about 30% by application of Broadcast. Moreover, although Update-based protocols attained the highest performance, the performance gap between Update-based protocols and Invalidate-based protocols is six to nine, and it turns out that Update-based protocols have little advantage against Invalidate-based protocols.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"52","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"47","bibliographicIssueDates":{"bibliographicIssueDate":"2004-12-02","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"123(2004-ARC-160)","bibliographicVolumeNumber":"2004"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":23268,"links":{}}