{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00023247","sets":["1164:1579:1598:1602"]},"path":["1602"],"owner":"1","recid":"23247","title":["クラスタ型スーパースカラプロセッサにおけるストア命令の早期発行手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2005-03-09"},"_buckets":{"deposit":"156de130-fb8c-484e-a198-0a94cc68810e"},"_deposit":{"id":"23247","pid":{"type":"depid","value":"23247","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"クラスタ型スーパースカラプロセッサにおけるストア命令の早期発行手法","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"クラスタ型スーパースカラプロセッサにおけるストア命令の早期発行手法"},{"subitem_title":"Reducing Issue Delay of Store Instructions on A clustered Microarchitecture","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2005-03-09","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学　工学部"},{"subitem_text_value":"東京大学大学院　情報理工学系研究科，科学技術振興機構"},{"subitem_text_value":"東京大学大学院　情報理工学系研究科"},{"subitem_text_value":"東京大学大学院　情報理工学系研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Technology, The University of Tokyo , Jpana Science and Technology Agency","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Technology, The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science and Technology, The University of Tokyo","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/23247/files/IPSJ-ARC04162034.pdf"},"date":[{"dateType":"Available","dateValue":"2007-03-09"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC04162034.pdf","filesize":[{"value":"346.3 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"dbf7dbcf-2341-47aa-9181-9a9f7958f2e6","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2005 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"渡邊, 翔太"},{"creatorName":"入江, 英嗣"},{"creatorName":"高田, 正法"},{"creatorName":"坂井, 修一"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shota, Watanabe","creatorNameLang":"en"},{"creatorName":"Hidetsugu, Irie","creatorNameLang":"en"},{"creatorName":"Masanori, Takada","creatorNameLang":"en"},{"creatorName":"Shuichi, Sakai","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"クラスタ型アーキテクチャは、実行コアを複数のクラスタに分散し、広い実行幅と高クロック動作の両立を目指している。本研究ではこのようなクラスタ型のスーパースカラプロセッサで従来よりも大きなボトルネックとなってしまうストア命令のIn-Orderかつ１サイクルに１つという発行の制限に着目し、ストア命令をより早い時刻に発行する手法を提案する。","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Clustered microarchitecture aims at coexistence of wider execution width and higher clock rate by distributing an execution core to clusters.In this paper, we focuse on the issue constraint of store instructions: Store instructions should be issued only one in a cycle following program order. This limit becomes a narrower bottleneck on clustered microarchitecture. Then we propose technique reducing issue delay of store instructions.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"204","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"199","bibliographicIssueDates":{"bibliographicIssueDate":"2005-03-09","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"19(2004-ARC-162)","bibliographicVolumeNumber":"2005"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":23247,"updated":"2025-01-22T20:31:07.712292+00:00","links":{},"created":"2025-01-18T22:54:42.269654+00:00"}