{"created":"2025-01-19T01:31:16.317454+00:00","updated":"2025-01-19T10:52:31.214556+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00231107","sets":["1164:2240:11176:11408"]},"path":["11408"],"owner":"44499","recid":"231107","title":["FPGA向け二相束データ式環状自己同期型パイプライン回路"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-28"},"_buckets":{"deposit":"b8bf170e-70c2-4611-a15e-d6b1575f4847"},"_deposit":{"id":"231107","pid":{"type":"depid","value":"231107","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"FPGA向け二相束データ式環状自己同期型パイプライン回路","author_link":["623398","623400","623399","623397","623401"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGA向け二相束データ式環状自己同期型パイプライン回路"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-11-28","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"筑波大学"},{"subitem_text_value":"筑波大学"},{"subitem_text_value":"筑波大学"},{"subitem_text_value":"高知工科大学"},{"subitem_text_value":"筑波大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"Kochi University of Technology","subitem_text_language":"en"},{"subitem_text_value":"University of Tsukuba","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/231107/files/IPSJ-HPC23192029.pdf","label":"IPSJ-HPC23192029.pdf"},"date":[{"dateType":"Available","dateValue":"2025-11-28"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC23192029.pdf","filesize":[{"value":"2.6 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"00c7627f-e39b-4393-a222-0dbd18d7d201","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"木下, 優"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"三宮, 秀次"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"吉川, 千里"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"岩田, 誠"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"西川, 博昭"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10463942","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8841","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"自己同期型パイプラインは,局所的なデータ転送により,パイプライン段水準の信号ゲーティングを自然に実現できる,電力対性能効率に優れた回路アーキテクチャである.既に,反復的あるいは再帰的な演算に加えてプログラム実行も実現できる環状のパイプラインを,回路水準での柔軟性を備えるとともに,入手性が高い商用 FPGA 上に実現可能とする,回路構成法が提案されている.しかし,これまでの構成法は,四相束データ式と呼ばれる,一回のデータ転送において制御に供する主な信号が四回遷移する動作様式をとる回路を対象としていた.本稿では,一回のデータ転送制御において,主な信号の遷移が二回で済み,高スループット化が期待できる,二相束データ式をとる回路構成法を提案する.環状パイプラインの基本的な機能である,二本から一本のパイプラインへの合流,一本から二本のパイプラインへの分流,さらに,データの複製や消去のそれぞれを実現するデータ転送制御回路とその設計手順を明らかにする.その上で,Intel 社製 Cyclone IV FPGA において,四相束データ式に比べ,データ転送制御回路の規模を約 24% 削減するとともに,最大で約 2 倍以上のパイプライン・スループットを実現できることを示す.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"研究報告ハイパフォーマンスコンピューティング(HPC)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-28","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"29","bibliographicVolumeNumber":"2023-HPC-192"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":231107,"links":{}}