{"created":"2025-01-19T01:31:15.932289+00:00","updated":"2025-01-19T10:52:35.585038+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00231103","sets":["1164:2240:11176:11408"]},"path":["11408"],"owner":"44499","recid":"231103","title":["逐次学習可能なグラフ分散表現のFPGAアクセラレータ"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-28"},"_buckets":{"deposit":"7f67fb9d-7933-4d0a-ba24-8d7527ad0ab0"},"_deposit":{"id":"231103","pid":{"type":"depid","value":"231103","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"逐次学習可能なグラフ分散表現のFPGAアクセラレータ","author_link":["623383","623387","623386","623388","623384","623385"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"逐次学習可能なグラフ分散表現のFPGAアクセラレータ"},{"subitem_title":"An FPGA-Based Accelerator for Graph Embedding using Sequential Training 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University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/231103/files/IPSJ-HPC23192025.pdf","label":"IPSJ-HPC23192025.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC23192025.pdf","filesize":[{"value":"2.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"14"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"e6f956d7-99cf-42c4-87ba-10619760cc79","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Institute of Electronics, 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つであるが，基本的に誤差逆伝播法を用いてバッチ学習を行うため，グラフ構造の時間的な変化に対応することができない．そのため逐次的に更新を行う場合，以前の学習結果が失われてしまい精度が低下する．これに対処するため，本研究ではオンライン学習アルゴリズムである OS-ELM を node2vec の学習モデルに適用し，逐次学習に対応させる．また，組み込み IoT 機器上での動作を見据えて，FPGA (Field-Programmable Gate Array) による高速化を提案する．FPGA 実装により，ARM Cortex-A53 CPUと比較して，最大 205.254 倍の高速化を達成した．また逐次学習タスクにおける精度評価では，既存の node2vec の学習モデルが精度低下を引き起こしたのに対し，提案モデルでは学習データの増大に伴うと思われる精度向上が見られた．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告ハイパフォーマンスコンピューティング（HPC）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-28","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"25","bibliographicVolumeNumber":"2023-HPC-192"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":231103,"links":{}}