{"created":"2025-01-19T01:31:13.841165+00:00","updated":"2025-01-19T10:53:03.483190+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00231081","sets":["1164:2240:11176:11408"]},"path":["11408"],"owner":"44499","recid":"231081","title":["Optimizing Matrix Multiplication on Arm Architectures"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-28"},"_buckets":{"deposit":"691f8d96-417b-4481-9737-bd0781d54dd8"},"_deposit":{"id":"231081","pid":{"type":"depid","value":"231081","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"Optimizing Matrix Multiplication on Arm Architectures","author_link":["623272","623269","623273","623265","623268","623267","623266","623271","623270","623264"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Optimizing Matrix Multiplication on Arm Architectures"},{"subitem_title":"Optimizing Matrix Multiplication on Arm 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Center for Computational Science","subitem_text_language":"en"},{"subitem_text_value":"Tokyo Institute of Technology","subitem_text_language":"en"},{"subitem_text_value":"RIKEN Center for Computational Science","subitem_text_language":"en"},{"subitem_text_value":"RIKEN Center for Computational Science","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/231081/files/IPSJ-HPC23192003.pdf","label":"IPSJ-HPC23192003.pdf"},"date":[{"dateType":"Available","dateValue":"2025-11-28"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-HPC23192003.pdf","filesize":[{"value":"434.9 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etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8841","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"This paper presents armGEMM, a novel approach aimed at enhancing the performance of irregular General Matrix Multiplication (GEMM) operations on popular Arm architectures. Designed to support a wide range of Arm processors, from edge devices to high-performance CPUs. armGEMM optimizes GEMM by intelligently combining fragments of auto-generated micro-kernels, incorporating hand-written optimizations to improve computational efficiency. We optimize the kernel pipeline by tuning the register reuse and the data load/store overlapping. In addition, we use a dynamic tiling scheme to generate balanced tile shapes, based on the shapes of the matrices. We build armGEMM on top of the TVM framework where our dynamic tiling scheme prunes the search space for TVM to identify the optimal combination of parameters for code optimization. Evaluations on five different classes of Arm chips demonstrate the advantages of armGEMM. In most cases involving irregular matrices, armGEMM outperforms state-of-the-art implementations like LIBXSMM, LibShalom, OpenBLAS, and Eigen.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This paper presents armGEMM, a novel approach aimed at enhancing the performance of irregular General Matrix Multiplication (GEMM) operations on popular Arm architectures. Designed to support a wide range of Arm processors, from edge devices to high-performance CPUs. armGEMM optimizes GEMM by intelligently combining fragments of auto-generated micro-kernels, incorporating hand-written optimizations to improve computational efficiency. We optimize the kernel pipeline by tuning the register reuse and the data load/store overlapping. In addition, we use a dynamic tiling scheme to generate balanced tile shapes, based on the shapes of the matrices. We build armGEMM on top of the TVM framework where our dynamic tiling scheme prunes the search space for TVM to identify the optimal combination of parameters for code optimization. Evaluations on five different classes of Arm chips demonstrate the advantages of armGEMM. In most cases involving irregular matrices, armGEMM outperforms state-of-the-art implementations like LIBXSMM, LibShalom, OpenBLAS, and Eigen.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"9","bibliographic_titles":[{"bibliographic_title":"研究報告ハイパフォーマンスコンピューティング(HPC)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-28","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicVolumeNumber":"2023-HPC-192"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":231081,"links":{}}