{"created":"2025-01-19T01:31:11.409412+00:00","updated":"2025-01-19T10:53:34.996374+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00231055","sets":["1164:1579:11081:11407"]},"path":["11407"],"owner":"44499","recid":"231055","title":["Using Intel oneAPI for multi-hybrid acceleration programming with GPU and FPGA coupling"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-28"},"_buckets":{"deposit":"f0db0476-a08c-416d-b744-8cff149b19fe"},"_deposit":{"id":"231055","pid":{"type":"depid","value":"231055","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"Using Intel oneAPI for multi-hybrid acceleration programming with GPU and FPGA coupling","author_link":["623170","623174","623175","623171","623172","623169","623168","623173"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Using Intel oneAPI for multi-hybrid acceleration programming with GPU and FPGA coupling"},{"subitem_title":"Using Intel oneAPI for multi-hybrid acceleration programming with GPU and FPGA coupling","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アクセラレータ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-11-28","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Degree Program in Systems and Information Engineering, University of Tsukuba"},{"subitem_text_value":"Center for Computational Sciences, University of Tsukuba/Degree Program in Systems and Information Engineering, University of Tsukuba"},{"subitem_text_value":"Center for Computational Sciences, University of Tsukuba/Degree Program in Systems and Information Engineering, University of Tsukuba"},{"subitem_text_value":"Center for Computational Sciences, University of Tsukuba/Degree Program in Systems and Information Engineering, University of Tsukuba"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Degree Program in Systems and Information Engineering, University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"Center for Computational Sciences, University of Tsukuba / Degree Program in Systems and Information Engineering, University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"Center for Computational Sciences, University of Tsukuba / Degree Program in Systems and Information Engineering, University of Tsukuba","subitem_text_language":"en"},{"subitem_text_value":"Center for Computational Sciences, University of Tsukuba / Degree Program in Systems and Information Engineering, University of Tsukuba","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/231055/files/IPSJ-ARC23255016.pdf","label":"IPSJ-ARC23255016.pdf"},"date":[{"dateType":"Available","dateValue":"2025-11-28"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC23255016.pdf","filesize":[{"value":"1.3 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"42969229-3ae9-4998-9144-68ba74ca3f4e","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Wentao, Liang"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Norihisa, Fujita"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ryohei, Kobayashi"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Taisuke, Boku"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Wentao, Liang","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Norihisa, Fujita","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Ryohei, Kobayashi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Taisuke, Boku","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8574","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Intel oneAPI is a programming framework that accepts various accelerators such as GPUs, FPGAs, and multi-core CPUs, with a focus on HPC applications. Users can apply their code written in a single language, DPC++, to this heterogeneous programming environment. However, in practice, it is not easy to apply to different accelerators, especially for non-Intel devices such as NVIDIA and AMD GPUs. We have successfully constructed a oneAPI environment set to utilize the single DPC++ programming to handle true multi-hetero acceleration including NVIDIA GPU and Intel FPGA simultaneously. In this paper, we will show how this is done and what kind of applications can be targeted.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Intel oneAPI is a programming framework that accepts various accelerators such as GPUs, FPGAs, and multi-core CPUs, with a focus on HPC applications. Users can apply their code written in a single language, DPC++, to this heterogeneous programming environment. However, in practice, it is not easy to apply to different accelerators, especially for non-Intel devices such as NVIDIA and AMD GPUs. We have successfully constructed a oneAPI environment set to utilize the single DPC++ programming to handle true multi-hetero acceleration including NVIDIA GPU and Intel FPGA simultaneously. In this paper, we will show how this is done and what kind of applications can be targeted.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"7","bibliographic_titles":[{"bibliographic_title":"研究報告システム・アーキテクチャ(ARC)"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-28","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"16","bibliographicVolumeNumber":"2023-ARC-255"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":231055,"links":{}}