{"id":23053,"updated":"2025-01-22T20:36:07.297920+00:00","links":{},"created":"2025-01-18T22:54:33.726037+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00023053","sets":["1164:1579:1592:1593"]},"path":["1593"],"owner":"1","recid":"23053","title":["An EDP Study on the Optimal Pipeline Depth for Pipeline Stage Unification Adoption"],"pubdate":{"attribute_name":"公開日","attribute_value":"2006-11-29"},"_buckets":{"deposit":"c50f57da-095a-42cf-aa45-38d24b3ff4c8"},"_deposit":{"id":"23053","pid":{"type":"depid","value":"23053","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"An EDP Study on the Optimal Pipeline Depth for Pipeline Stage Unification Adoption","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"An EDP Study on the Optimal Pipeline Depth for Pipeline Stage Unification Adoption"},{"subitem_title":"An EDP Study on the Optimal Pipeline Depth for Pipeline Stage Unification Adoption","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2006-11-29","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Informatics  Kyoto University"},{"subitem_text_value":"Graduate School of Informatics  Kyoto University"},{"subitem_text_value":"Graduate School of Information Science  Nara Institute of Science and Technology"},{"subitem_text_value":"Graduate School of Engineering  Fukui University"},{"subitem_text_value":"Graduate School of Informatics  Kyoto University"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Graduate School of Informatics, Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Informatics, Kyoto University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Information Science, Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Engineering, Fukui University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Informatics, Kyoto University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/23053/files/IPSJ-ARC06170008.pdf"},"date":[{"dateType":"Available","dateValue":"2008-11-29"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC06170008.pdf","filesize":[{"value":"1.1 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"b687acce-07fe-4fe9-9667-5b3e436bc8d9","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2006 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Jun, YANO"},{"creatorName":"Hajime, SHIMADA"},{"creatorName":"Yasuhiko, NAKASHIMA"},{"creatorName":"Shin-ichiroMORI"},{"creatorName":"Shinji, TOMITA"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Jun, YANO","creatorNameLang":"en"},{"creatorName":"Hajime, SHIMADA","creatorNameLang":"en"},{"creatorName":"Yasuhiko, NAKASHIMA","creatorNameLang":"en"},{"creatorName":"Shin-ichiro, MORI","creatorNameLang":"en"},{"creatorName":"Shinji, TOMITA","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"To find optimal pipeline design point by considering both performance and power objectives has been one hot spot in recent researches. However  we found that previous papers did not consider deepening or shrinking pipeline depth dynamically during program execution. In this paper  with the adoption of the previously proposed Pipeline Stage Unification (PSU) method  we studied the relationship between power/performance and pipeline depth in processors with a pipeline of multi-usable depths. Our evaluation results of SPECint2000 benchmarks show that the 24-stage PSU enabled pipeline can achieve the smallest Energy-Delay-Product (EDP). Moreover  it can obtain more EDP reduction  compared to the processors with fixed 12-stage pipeline  which is the optimal pipeline depth among fixed depth pipelines.","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"To find optimal pipeline design point by considering both performance and power objectives has been one hot spot in recent researches. However, we found that previous papers did not consider deepening or shrinking pipeline depth dynamically during program execution. In this paper, with the adoption of the previously proposed Pipeline Stage Unification (PSU) method, we studied the relationship between power/performance and pipeline depth in processors with a pipeline of multi-usable depths. Our evaluation results of SPECint2000 benchmarks show that the 24-stage PSU enabled pipeline can achieve the smallest Energy-Delay-Product (EDP). Moreover, it can obtain more EDP reduction, compared to the processors with fixed 12-stage pipeline, which is the optimal pipeline depth among fixed depth pipelines.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"48","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"43","bibliographicIssueDates":{"bibliographicIssueDate":"2006-11-29","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"127(2006-ARC-170)","bibliographicVolumeNumber":"2006"}]},"relation_version_is_last":true,"weko_creator_id":"1"}}