@techreport{oai:ipsj.ixsq.nii.ac.jp:00023053,
 author = {Jun, YANO and Hajime, SHIMADA and Yasuhiko, NAKASHIMA and Shin-ichiroMORI and Shinji, TOMITA and Jun, YANO and Hajime, SHIMADA and Yasuhiko, NAKASHIMA and Shin-ichiro, MORI and Shinji, TOMITA},
 issue = {127(2006-ARC-170)},
 month = {Nov},
 note = {To find optimal pipeline design point by considering both performance and power objectives has been one hot spot in recent researches. However  we found that previous papers did not consider deepening or shrinking pipeline depth dynamically during program execution. In this paper  with the adoption of the previously proposed Pipeline Stage Unification (PSU) method  we studied the relationship between power/performance and pipeline depth in processors with a pipeline of multi-usable depths. Our evaluation results of SPECint2000 benchmarks show that the 24-stage PSU enabled pipeline can achieve the smallest Energy-Delay-Product (EDP). Moreover  it can obtain more EDP reduction  compared to the processors with fixed 12-stage pipeline  which is the optimal pipeline depth among fixed depth pipelines., To find optimal pipeline design point by considering both performance and power objectives has been one hot spot in recent researches. However, we found that previous papers did not consider deepening or shrinking pipeline depth dynamically during program execution. In this paper, with the adoption of the previously proposed Pipeline Stage Unification (PSU) method, we studied the relationship between power/performance and pipeline depth in processors with a pipeline of multi-usable depths. Our evaluation results of SPECint2000 benchmarks show that the 24-stage PSU enabled pipeline can achieve the smallest Energy-Delay-Product (EDP). Moreover, it can obtain more EDP reduction, compared to the processors with fixed 12-stage pipeline, which is the optimal pipeline depth among fixed depth pipelines.},
 title = {An EDP Study on the Optimal Pipeline Depth for Pipeline Stage Unification Adoption},
 year = {2006}
}