An EDP Study on the Optimal Pipeline Depth for Pipeline Stage Unification Adoption

• Item type: SIG Technical Reports(1)
• 公開日: 2006-11-29
• タイトル: An EDP Study on the Optimal Pipeline Depth for Pipeline Stage Unification Adoption
• タイトル / 言語: en
• タイトル: An EDP Study on the Optimal Pipeline Depth for Pipeline Stage Unification Adoption
• 言語: eng
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Informatics Kyoto University
• 著者所属: Graduate School of Informatics Kyoto University
• 著者所属: Graduate School of Information Science Nara Institute of Science and Technology
• 著者所属: Graduate School of Engineering Fukui University
• 著者所属: Graduate School of Informatics Kyoto University
• 著者所属(英): en
• 著者所属(英): Graduate School of Informatics, Kyoto University
• 著者所属(英): en
• 著者所属(英): Graduate School of Informatics, Kyoto University
• 著者所属(英): en
• 著者所属(英): Graduate School of Information Science, Nara Institute of Science and Technology
• 著者所属(英): en
• 著者所属(英): Graduate School of Engineering, Fukui University
• 著者所属(英): en
• 著者所属(英): Graduate School of Informatics, Kyoto University
• 著者名: Jun, YANO; Hajime, SHIMADA; Yasuhiko, NAKASHIMA; Shin-ichiroMORI; Shinji, TOMITA
• 著者名(英): Jun, YANO; Hajime, SHIMADA; Yasuhiko, NAKASHIMA; Shin-ichiro, MORI; Shinji, TOMITA
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: To find optimal pipeline design point by considering both performance and power objectives has been one hot spot in recent researches. However we found that previous papers did not consider deepening or shrinking pipeline depth dynamically during program execution. In this paper with the adoption of the previously proposed Pipeline Stage Unification (PSU) method we studied the relationship between power/performance and pipeline depth in processors with a pipeline of multi-usable depths. Our evaluation results of SPECint2000 benchmarks show that the 24-stage PSU enabled pipeline can achieve the smallest Energy-Delay-Product (EDP). Moreover it can obtain more EDP reduction compared to the processors with fixed 12-stage pipeline which is the optimal pipeline depth among fixed depth pipelines.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: To find optimal pipeline design point by considering both performance and power objectives has been one hot spot in recent researches. However, we found that previous papers did not consider deepening or shrinking pipeline depth dynamically during program execution. In this paper, with the adoption of the previously proposed Pipeline Stage Unification (PSU) method, we studied the relationship between power/performance and pipeline depth in processors with a pipeline of multi-usable depths. Our evaluation results of SPECint2000 benchmarks show that the 24-stage PSU enabled pipeline can achieve the smallest Energy-Delay-Product (EDP). Moreover, it can obtain more EDP reduction, compared to the processors with fixed 12-stage pipeline, which is the optimal pipeline depth among fixed depth pipelines.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10096105
• 書誌情報: 情報処理学会研究報告計算機アーキテクチャ（ARC）; 巻 2006, 号 127(2006-ARC-170), p. 43-48, 発行日 2006-11-29
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会