{"created":"2025-01-19T01:28:49.105876+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00229577","sets":["6504:11436:11437"]},"path":["11437"],"owner":"44499","recid":"229577","title":["マルチインスタンスGPUを用いた推論ワークロードのクラスタスケジューリング"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-02-16"},"_buckets":{"deposit":"6659277c-f172-412d-a79a-7441c13df317"},"_deposit":{"id":"229577","pid":{"type":"depid","value":"229577","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"マルチインスタンスGPUを用いた推論ワークロードのクラスタスケジューリング","author_link":["617529","617528"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"マルチインスタンスGPUを用いた推論ワークロードのクラスタスケジューリング"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"コンピュータシステム","subitem_subject_scheme":"Other"}]},"item_type_id":"22","publish_date":"2023-02-16","item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_22_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"北大"},{"subitem_text_value":"北大"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/229577/files/IPSJ-Z85-6J-05.pdf","label":"IPSJ-Z85-6J-05.pdf"},"date":[{"dateType":"Available","dateValue":"2023-11-17"}],"format":"application/pdf","filename":"IPSJ-Z85-6J-05.pdf","filesize":[{"value":"243.0 kB"}],"mimetype":"application/pdf","accessrole":"open_date","version_id":"57c22f9c-9dc1-45c9-8421-7140694cd6d3","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Information Processing Society of Japan"}]},"item_22_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"三井, 郁央"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"杉木, 章義"}],"nameIdentifiers":[{}]}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_5794","resourcetype":"conference paper"}]},"item_22_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN00349328","subitem_source_identifier_type":"NCID"}]},"item_22_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"NVIDIA マルチインスタンスGPU(MIG)は,2020年にNVIDIAによって発表されたGPUの新たな分割機構である.この技術は従来のMulti Process ServiceやvGPUと異なり,障害分離性を保ったまま複数のジョブを同一GPU内で同時に実行でき,1つのジョブあたり1つのGPUを使用する場合より,コストを削減することが可能である.本研究では,荷物の組み合わせを考慮したビンパッキング問題に還元することにより,使用するGPU数を最小化するスケジューラを作成した.シミュレーションを行い,インスタンスの分割を固定した場合と比較した.","subitem_description_type":"Other"}]},"item_22_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"90","bibliographic_titles":[{"bibliographic_title":"第85回全国大会講演論文集"}],"bibliographicPageStart":"89","bibliographicIssueDates":{"bibliographicIssueDate":"2023-02-16","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"2023"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":229577,"updated":"2025-01-19T11:30:19.741849+00:00","links":{}}