A Temporal Correlation Based Port Combination Methodology for Application-Specific Networks-on-chip on FPGAs

• Item type: SIG Technical Reports(1)
• 公開日: 2007-08-02
• タイトル: A Temporal Correlation Based Port Combination Methodology for Application-Specific Networks-on-chip on FPGAs
• タイトル / 言語: en
• タイトル: A Temporal Correlation Based Port Combination Methodology for Application-Specific Networks-on-chip on FPGAs
• 言語: eng
• 資源タイプ / 資源タイプ識別子: http://purl.org/coar/resource_type/c_18gh
• 資源タイプ: technical report
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属: National Institute of Informatics
• 著者所属: Graduate School of Science and Technology Keio University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者所属(英): en
• 著者所属(英): National Institute of Informatics
• 著者所属(英): en
• 著者所属(英): Graduate School of Science and Technology, Keio University
• 著者名: 王, 代涵; 松谷, 宏紀; 鯉渕, 道紘; 天野, 英晴
• 著者名(英): Daihan, Wang; Hiroki, Matsutani; Michihiro, Koibuchi; Hideharu, Amano
• 論文抄録 / 内容記述タイプ: Other
• 論文抄録 / 内容記述: A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate the algorithm automatically makes the port combination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology it does not affect the design of the other layers such as task mapping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application the algorithm can save 55% of the hardware amount without performance degradation while the non-temporal correlation algorithm suffers from 30% performance loss.
• 論文抄録(英) / 内容記述タイプ: Other
• 論文抄録(英) / 内容記述: A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize required hardware amount. Given the traffic characteristics of the target application and the expected hardware amount reduction rate, the algorithm automatically makes the port combination plan for the networks. Since the port combination technique has the advantage of almost keeping the topology, it does not affect the design of the other layers, such as task mapping and scheduling. The algorithm shows much better efficiency than the algorithm without temporal correlation. For the multimedia stream processing application, the algorithm can save 55% of the hardware amount without performance degradation, while the non-temporal correlation algorithm suffers from 30% performance loss.
• 書誌レコードID / 収録物識別子タイプ: NCID
• 書誌レコードID / 収録物識別子: AN10096105
• 書誌情報: 情報処理学会研究報告計算機アーキテクチャ（ARC）; 巻 2007, 号 79(2007-ARC-174), p. 133-138, 発行日 2007-08-02
• Notice: SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc.
• 出版者 / 言語: ja
• 出版者: 情報処理学会