{"updated":"2025-01-22T20:39:24.576868+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00022931","sets":["1164:1579:1585:1588"]},"path":["1588"],"owner":"1","recid":"22931","title":["大規模科学技術計算向けSIMD拡張スカラプロセッサの提案とその評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2007-08-01"},"_buckets":{"deposit":"9f0fd537-3152-442a-b2ca-0a0e5774c649"},"_deposit":{"id":"22931","pid":{"type":"depid","value":"22931","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"大規模科学技術計算向けSIMD拡張スカラプロセッサの提案とその評価","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"大規模科学技術計算向けSIMD拡張スカラプロセッサの提案とその評価"},{"subitem_title":"Proposal and Evaluation of SIMD Extended Scalar Processor for　Large-scale Scientific Applications","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2007-08-01","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"富士通株式会社"},{"subitem_text_value":"富士通株式会社"},{"subitem_text_value":"富士通株式会社"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Fujitsu, Ltd","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu, Ltd","subitem_text_language":"en"},{"subitem_text_value":"Fujitsu, Ltd","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/22931/files/IPSJ-ARC07174011.pdf"},"date":[{"dateType":"Available","dateValue":"2009-08-01"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC07174011.pdf","filesize":[{"value":"510.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"215f72d8-b5f6-495d-81e7-581117c96b3f","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2007 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"山村, 周史"},{"creatorName":"青木, 孝"},{"creatorName":"安藤寿茂"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"SHUJI, YAMAMURA","creatorNameLang":"en"},{"creatorName":"TAKASHI, AOKI","creatorNameLang":"en"},{"creatorName":"HISASHIGE, ANDO","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"我々は，ペタスケールシステム向けのプロセッサアーキテクチャの検討を行っている．ペタスケール規模の科学技術計算アプリケーションを高速に実行するためには，大量の浮動小数点演算を高効率で処理できなければならない．これを実現するために，我々は，既存のスカラプロセッサに対して， SIMD 演算ユニットを拡張装備するアーキテクチャを提案する． HPL および PHASE の主要計算ルーチンを対象として，シミュレーションにより本アーキテクチャの性能評価を行い，その有効性について述べる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"A processor for a peta-scale supercomputer requires achieving high floating point performance with high energy efficiency. To meet these requirements, we propose an architecture with the combination of a high performance superscalar processor core and wide SIMD processing elements. In this paper, we evaluate its performance and effectiveness with an architecture simulator using math kernels of HPL and PHASE.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"66","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"61","bibliographicIssueDates":{"bibliographicIssueDate":"2007-08-01","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"79(2007-ARC-174)","bibliographicVolumeNumber":"2007"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"created":"2025-01-18T22:54:28.330985+00:00","id":22931,"links":{}}