{"metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00022914","sets":["1164:1579:1585:1587"]},"path":["1587"],"owner":"1","recid":"22914","title":["細粒度命令分解と小品種セルによる高信頼化アーキテクチャの提案"],"pubdate":{"attribute_name":"公開日","attribute_value":"2007-11-22"},"_buckets":{"deposit":"3bfbbcdf-9564-484d-bb7e-da2b180e88e5"},"_deposit":{"id":"22914","pid":{"type":"depid","value":"22914","revision_id":0},"owners":[1],"status":"published","created_by":1},"item_title":"細粒度命令分解と小品種セルによる高信頼化アーキテクチャの提案","author_link":["0","0"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"細粒度命令分解と小品種セルによる高信頼化アーキテクチャの提案"},{"subitem_title":"A Highly Reliable Architecture with a Fine-grained Instruction Decomposition and a Small Variety of Standard Cells","subitem_title_language":"en"}]},"item_type_id":"4","publish_date":"2007-11-22","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"奈良先端科学技術大学院大学"},{"subitem_text_value":"奈良先端科学技術大学院大学"},{"subitem_text_value":"奈良先端科学技術大学院大学"},{"subitem_text_value":"奈良先端科学技術大学院大学"},{"subitem_text_value":"奈良先端科学技術大学院大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Nara Institute of Science and Technology","subitem_text_language":"en"},{"subitem_text_value":"Nara Institute of Science and Technology","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/22914/files/IPSJ-ARC07175012.pdf"},"date":[{"dateType":"Available","dateValue":"2009-11-22"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-ARC07175012.pdf","filesize":[{"value":"493.1 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"16"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"d49865b6-b0a8-4bc5-877f-20610de09646","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2007 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"鈴木, 一範"},{"creatorName":"中田, 尚"},{"creatorName":"中西, 正樹"},{"creatorName":"山下, 茂"},{"creatorName":"中島, 康彦"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kazunori, SUZUKI","creatorNameLang":"en"},{"creatorName":"Takashi, NAKADA","creatorNameLang":"en"},{"creatorName":"Masaki, NAKANISHI","creatorNameLang":"en"},{"creatorName":"Shigeru, YAMASHITA","creatorNameLang":"en"},{"creatorName":"Yasuhiko, NAKASHIMA","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN10096105","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年のトランジスタ製造のプロセス微細化によって，トランジスタの性能ばらつきが無視できない問題となっている．ばらつきを抑える手法として，セル内のトランジスタを規則的に配置するという方法がある．本論文では  トランジスタを規則的に配置したセルを提案する．このセルは PMOS と NMOS を組み合わせたものが基本単位として構成されている．我々の提案したセルは，従来のセルに比べて壊れにくく，また故障を検知する機能を備えている．次に，このセルを組み合わせた高信頼性の演算器を提案した．提案した演算器と命令分解機構を組み合わせることにより従来にない高信頼化アーキテクチャが実現できると考えている．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Recently, process deviation causes transistor variation. It is known that transistor variation can be reduced by arranging transistors regularly. In this paper, we propose new standard cells in which transistors are arranged regularity in order to control variation. These cells are composed by pairs of PMOS and NMOS. The proposed cells are more robust against transistor faults and can also detect them. Next, we propese highly reliable arithmetic circuit by using our cells. We also show that highly reliable architecture can be constructed by this circuit and instruction decomposition circuit.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"66","bibliographic_titles":[{"bibliographic_title":"情報処理学会研究報告計算機アーキテクチャ（ARC）"}],"bibliographicPageStart":"61","bibliographicIssueDates":{"bibliographicIssueDate":"2007-11-22","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"115(2007-ARC-175)","bibliographicVolumeNumber":"2007"}]},"relation_version_is_last":true,"weko_creator_id":"1"},"id":22914,"updated":"2025-01-22T20:40:29.006268+00:00","links":{},"created":"2025-01-18T22:54:27.580597+00:00"}