{"created":"2025-01-19T01:28:07.075673+00:00","updated":"2025-01-19T11:38:56.224149+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00228989","sets":["1164:2822:11181:11358"]},"path":["11358"],"owner":"44499","recid":"228989","title":["FPGAを対象とした高速な32ビットおよび48ビットの乗算器"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-09"},"_buckets":{"deposit":"997889d2-c024-40b4-ba1b-65678b38e164"},"_deposit":{"id":"228989","pid":{"type":"depid","value":"228989","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"FPGAを対象とした高速な32ビットおよび48ビットの乗算器","author_link":["615028","615030","615029","615031"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"FPGAを対象とした高速な32ビットおよび48ビットの乗算器"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アーキテクチャ","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-11-09","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"立命館大学"},{"subitem_text_value":"立命館大学"},{"subitem_text_value":"大阪大学"},{"subitem_text_value":"立命館大学"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/228989/files/IPSJ-EMB23064001.pdf","label":"IPSJ-EMB23064001.pdf"},"date":[{"dateType":"Available","dateValue":"2025-11-09"}],"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-EMB23064001.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"660","billingrole":"5"},{"tax":["include_tax"],"price":"330","billingrole":"6"},{"tax":["include_tax"],"price":"0","billingrole":"42"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_date","version_id":"da4a6507-4293-4848-bc56-9f89923fc97c","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Information Processing Society of Japan"}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"大橋, 和奏"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"山口, 葵生"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"西川, 広記"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"冨山, 宏之"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA12149313","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-868X","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"近年，画像処理や人工知能などの分野で演算処理の速い乗算器の需要が高まっている．そこで本論文では，Xilinx 標準の乗算器 IP を改良した 32 ビット乗算器と 48 ビット乗算器を提案する．Xilinx 社 Vivado を用いて乗算器の遅延時間，消費電力を測定した．測定した結果，改良した乗算器は遅延時間が最大で 20％ 削減されることが確認できた．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"2","bibliographic_titles":[{"bibliographic_title":"研究報告組込みシステム（EMB）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-09","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicVolumeNumber":"2023-EMB-64"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":228989,"links":{}}