{"created":"2025-01-19T01:28:03.067298+00:00","updated":"2025-01-19T11:40:22.152955+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00228919","sets":["1164:2036:11089:11372"]},"path":["11372"],"owner":"44499","recid":"228919","title":["同期式回路設計支援環境におけるMuller’s C-elementの実装に関する一考察"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-10"},"_buckets":{"deposit":"58de3500-045a-4cb3-bd28-afef4f332693"},"_deposit":{"id":"228919","pid":{"type":"depid","value":"228919","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"同期式回路設計支援環境におけるMuller’s C-elementの実装に関する一考察","author_link":["614759","614758"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"同期式回路設計支援環境におけるMuller’s C-elementの実装に関する一考察"},{"subitem_title":"A Study on the Implementation of Muller’s C-element in Synchronous Circuit Design Environment","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"アルゴリズム，VLSI試作・実用化","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-11-10","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"弘前大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Hirosaki University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/228919/files/IPSJ-SLDM23204052.pdf","label":"IPSJ-SLDM23204052.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM23204052.pdf","filesize":[{"value":"913.7 kB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"1fba5ed0-239a-46bd-a29e-cdd2f529a6d2","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"今井, 雅"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Masashi, Imai","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"Muller の C 素子は，非同期式回路の実現において，信号と信号の待ち合わせを行うためにしばしば用いられる基本素子である．C 素子の実装方式として様々な構成が提案されているが，使用できる製造プロセス，設計支援環境によっては選択することのできない構成もある．本稿では，仕様で定められた制約に応じて，スタンダードセルライブラリに含まれる素子のみを用いた Muller の C 素子の設計方法や，オリジナルセルの設計も可能な環境における C 素子の構成方法等について紹介する．その中の一つとして，D-latch を用いた C 素子の構成について新たに提案する．提案した構成は，複合ゲートや基本論理素子を用いる構成と比較して，トランジスタ数としては約 2 倍となるが，遅延は 1.2 倍程度のオーバーヘッドとなることが確認された．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"Muller’s C-element is a basic component often used to rendezvous signals in asynchronous circuit designs. A lot of implementation methods have been proposed and well studied. However, several structures may not be selectable depending on the selected manufacturing process and EDA tools. In this paper, we discuss how to design Muller’s C-element according to the constraints specified using only standard cells in the selected cell library. The transistor level circuit structures are also discussed under the assumption which can design original cells. A new structure of a C-element using a D-latch will be also proposed. It is confirmed that the proposed structure has approximately twice the number of transistors compared to the traditional structures and the delay overhead is about 1.2 times larger than those.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-10","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"52","bibliographicVolumeNumber":"2023-SLDM-204"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":228919,"links":{}}