{"created":"2025-01-19T01:28:02.779912+00:00","updated":"2025-01-19T11:40:27.570634+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00228914","sets":["1164:2036:11089:11372"]},"path":["11372"],"owner":"44499","recid":"228914","title":["MISCプロセッサの光再構成型ゲートアレイVLSIへの実装と最大動作周波数評価"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-10"},"_buckets":{"deposit":"6985688c-3360-4bb5-8168-81e4b98ea759"},"_deposit":{"id":"228914","pid":{"type":"depid","value":"228914","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"MISCプロセッサの光再構成型ゲートアレイVLSIへの実装と最大動作周波数評価","author_link":["614735","614733","614734","614737","614732","614736"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"MISCプロセッサの光再構成型ゲートアレイVLSIへの実装と最大動作周波数評価"},{"subitem_title":"Maximum operating clock frequency evaluation of Mono Instruction Set Computers on an optically reconfigurable gate array VLSI","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGA応用","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-11-10","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"岡山大学工学部情報系学科"},{"subitem_text_value":"岡山大学大学院環境生命自然科学研究科"},{"subitem_text_value":"岡山大学大学院環境生命自然科学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, Department of Information Technology, Okayama University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Technology Environmental, life, natural Science and Technology Okayama University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Technology Environmental, life, natural Science and ","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/228914/files/IPSJ-SLDM23204047.pdf","label":"IPSJ-SLDM23204047.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM23204047.pdf","filesize":[{"value":"1.4 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"ba7fce9b-b92d-43a7-aaa0-b189c1bc2d89","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"今井, 颯真"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"渡邊, 実"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"渡邊, 誠也"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Imai, Soma","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Minoru, Watanabe","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Nobuya, Watanabe","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"我々は数ナノ秒以内に再構成可能な光学的に再構成可能なゲートアレイ VLSI を開発している．この高速動的再構成を活用すれば，単一の命令のみしか持たない Mono Insyruction Set Computer (MISC) アーキテクチャの実装も，汎用性を損なうことなく可能になる．本稿では Mono Insyruction Set Computer (MISC) アーキテクチャを 0.18µm CMOS プロセス光再構成型ゲートアレイ VLSI に実装した結果について述べる．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"We have been developing an optically reconfigurable gate array which can be reconfigured within a few nanoseconds. Exploiting such high-speed dynamic reconfiguration, mono instruction set computer architecture can be used for variety of software algorithms without any restriction. This paper presents an evaluation result of the mono instruction set computer (MISC) architecture implemented onto an optically reconfigurable gate array VLSI.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"4","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-10","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"47","bibliographicVolumeNumber":"2023-SLDM-204"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":228914,"links":{}}