{"updated":"2025-01-19T11:40:28.760179+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00228913","sets":["1164:2036:11089:11372"]},"path":["11372"],"owner":"44499","recid":"228913","title":["ベイジアンニューラルネットワークのベルヌーイ近似を適用したハードウェア軽量化手法"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-10"},"_buckets":{"deposit":"aeefe7cf-dc6f-43e5-954c-48b1b28b67c7"},"_deposit":{"id":"228913","pid":{"type":"depid","value":"228913","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"ベイジアンニューラルネットワークのベルヌーイ近似を適用したハードウェア軽量化手法","author_link":["614728","614726","614730","614729","614731","614727"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"ベイジアンニューラルネットワークのベルヌーイ近似を適用したハードウェア軽量化手法"},{"subitem_title":"Hardware Compression Method Applying Bernoulli Approximation for Bayesian Neural Networks","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"FPGA応用","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-11-10","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"北海道大学大学院情報科学院"},{"subitem_text_value":"北海道大学大学院情報科学研究院"},{"subitem_text_value":"北海道大学大学院情報科学研究院"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/228913/files/IPSJ-SLDM23204046.pdf","label":"IPSJ-SLDM23204046.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM23204046.pdf","filesize":[{"value":"3.5 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"2a976674-6e49-47bb-95c4-29e3232986e5","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"齋藤, 大成"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"安藤, 洸太"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"浅井, 哲也"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Taisei, Saito","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kota, Ando","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Tetsuya, Asai","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"本研究はベイズ深層学習のアルゴリズムを効率的に軽量化し，それを FPGA へ実装する手法に焦点を当てている．変分推論法と量子化技術の二値化を組み合わせ，モデルの計算量及びメモリ量を削減し FPGA 上で低リソースでの実装を可能とした．本研究の実験結果は，モデルの量子化が性能と FPGA のリソースへどのように貢献するかを示し，計算資源が限られた環境でのベイズ深層学習の実用性を検証する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"This study focuses on efficiently lightweighting Bayesian deep learning algorithms and implementing them on FPGA. It combines variational inference techniques with one of the quantization techniques: binarization, reducing both computational and memory requirements to enable implementation on FPGA with limited resources. The experimental results of this research demonstrate the contribution of model quantization to performance and FPGA resource usage, verifying the practicality of Bayesian deep learning in resource-constrained environments.","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-10","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"46","bibliographicVolumeNumber":"2023-SLDM-204"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"created":"2025-01-19T01:28:02.722968+00:00","id":228913,"links":{}}