{"created":"2025-01-19T01:28:02.550639+00:00","updated":"2025-01-19T11:40:31.870050+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00228910","sets":["1164:2036:11089:11372"]},"path":["11372"],"owner":"44499","recid":"228910","title":["SLM細粒度再構成ロジックにおける構成情報の圧縮"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-10"},"_buckets":{"deposit":"82714ec1-9231-4c6f-9216-46266c78693a"},"_deposit":{"id":"228910","pid":{"type":"depid","value":"228910","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"SLM細粒度再構成ロジックにおける構成情報の圧縮","author_link":["614714","614711","614712","614713","614715","614708","614709","614716","614710","614707"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"SLM細粒度再構成ロジックにおける構成情報の圧縮"},{"subitem_title":"Configuration Data Compression for SLM Fine-grained Reconfigurable Logic","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"新FPGAの設計と検証","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-11-10","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"東京大学"},{"subitem_text_value":"慶應義塾大学理工学部"},{"subitem_text_value":"熊本大学"},{"subitem_text_value":"熊本大学"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Dept. of ICS, Keio University","subitem_text_language":"en"},{"subitem_text_value":"The University of Tokyo","subitem_text_language":"en"},{"subitem_text_value":"Dept. of ICS, Keio University","subitem_text_language":"en"},{"subitem_text_value":"Kumamoto University","subitem_text_language":"en"},{"subitem_text_value":"Kumamoto University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/228910/files/IPSJ-SLDM23204043.pdf","label":"IPSJ-SLDM23204043.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM23204043.pdf","filesize":[{"value":"1.2 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"1bd5da8c-545c-4d5f-90d4-dfb9ab859be4","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"高木, 颯平"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"小島, 拓也"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"天野, 英晴"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"久我, 守弘"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"飯田, 全広"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Souhei, Takagi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Takuya, Kojima","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hideharu, Amano","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Kuga, Morihiro","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Masahiro, Iida","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"SLM (Scalable Logic Module) は，熊本大学が開発した細粒度再構成ロジックであり，構成情報量が小さく，これによりロジックセルの面積も小さい特徴がある．我々は，このSLM，CPU，スイッチ，メモリを内蔵した新しい FPGA を開発している．このチップでは SLM の構成情報量の小ささを利用し，内部メモリ上に複数の構成情報を蓄え，高速に入れ替える機能を持つ．本稿では，構成情報を圧縮することで，さらに多くの構成情報データを格納するための手法を提案する．この圧縮法は，チップ内部で高速に伸長が可能であり，簡単なハードウェアで実装が可能でなければならない．また，対象となる SLM 再構成ロジックの構成情報は，内部のモジュールで同じパターンが複数回出現しやすい等の特徴を持つ．そこで，今回はこれらの条件に沿った圧縮手法として DMC (Duplicated Module Compression) を提案する．DMC では複数回登場するパターンを辞書に登録することで，Run length 圧縮を行う．加えて伸長回路については，NANGATE45nm プロセスを想定した論理合成を Synopsys 社の Design Compiler N-2017.09-SP1 で行なった．その結果，伸長回路単体では 1GHz で動作するように遅延を設定した上で 708.9µ????2 という小さな回路面積であることがわかった．","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"6","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-10","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"43","bibliographicVolumeNumber":"2023-SLDM-204"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":228910,"links":{}}