{"created":"2025-01-19T01:28:02.435470+00:00","updated":"2025-01-19T11:40:33.916444+00:00","metadata":{"_oai":{"id":"oai:ipsj.ixsq.nii.ac.jp:00228908","sets":["1164:2036:11089:11372"]},"path":["11372"],"owner":"44499","recid":"228908","title":["光再構成アーキテクチャを用いたウエハースケールVLSIの実現性"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-11-10"},"_buckets":{"deposit":"a37b6836-7e69-45dc-8067-4d3c350bbbcd"},"_deposit":{"id":"228908","pid":{"type":"depid","value":"228908","revision_id":0},"owners":[44499],"status":"published","created_by":44499},"item_title":"光再構成アーキテクチャを用いたウエハースケールVLSIの実現性","author_link":["614694","614693","614695","614697","614696","614698"],"item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"光再構成アーキテクチャを用いたウエハースケールVLSIの実現性"},{"subitem_title":"A wafer-scale VLSI realization using optical reconfiguration architecture","subitem_title_language":"en"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"新FPGAの設計と検証","subitem_subject_scheme":"Other"}]},"item_type_id":"4","publish_date":"2023-11-10","item_4_text_3":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"岡山大学工学部情報系学科"},{"subitem_text_value":"岡山大学大学院環境生命自然科学研究科"},{"subitem_text_value":"岡山大学大学院環境生命自然科学研究科"}]},"item_4_text_4":{"attribute_name":"著者所属(英)","attribute_value_mlt":[{"subitem_text_value":"Faculty of Engineering, Department of Information Technology, Okayama University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Technology Environmental, life, natural Science and Technology Okayama University","subitem_text_language":"en"},{"subitem_text_value":"Graduate School of Technology Environmental, life, natural Science and Technology Okayama University","subitem_text_language":"en"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_publisher":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"情報処理学会","subitem_publisher_language":"ja"}]},"publish_status":"0","weko_shared_id":-1,"item_file_price":{"attribute_name":"Billing file","attribute_type":"file","attribute_value_mlt":[{"url":{"url":"https://ipsj.ixsq.nii.ac.jp/record/228908/files/IPSJ-SLDM23204041.pdf","label":"IPSJ-SLDM23204041.pdf"},"format":"application/pdf","billing":["billing_file"],"filename":"IPSJ-SLDM23204041.pdf","filesize":[{"value":"2.9 MB"}],"mimetype":"application/pdf","priceinfo":[{"tax":["include_tax"],"price":"0","billingrole":"10"},{"tax":["include_tax"],"price":"0","billingrole":"44"}],"accessrole":"open_login","version_id":"1d167f3b-7ca9-4b01-9488-6a5f541836df","displaytype":"detail","licensetype":"license_note","license_note":"Copyright (c) 2023 by the Institute of Electronics, Information and Communication Engineers This SIG report is only available to those in membership of the SIG."}]},"item_4_creator_5":{"attribute_name":"著者名","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"高田, 睦士"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"渡邊, 実"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"渡邊, 誠也"}],"nameIdentifiers":[{}]}]},"item_4_creator_6":{"attribute_name":"著者名(英)","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Takata, Atsushi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Minoru, Watanabe","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Nobuya, Watanabe","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_4_source_id_9":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA11451459","subitem_source_identifier_type":"NCID"}]},"item_4_textarea_12":{"attribute_name":"Notice","attribute_value_mlt":[{"subitem_textarea_value":"SIG Technical Reports are nonrefereed and hence may later appear in any journals, conferences, symposia, etc."}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourceuri":"http://purl.org/coar/resource_type/c_18gh","resourcetype":"technical report"}]},"item_4_source_id_11":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"2188-8639","subitem_source_identifier_type":"ISSN"}]},"item_4_description_7":{"attribute_name":"論文抄録","attribute_value_mlt":[{"subitem_description":"スーパーコンピュータやデータセンターでは多数の CPU が 1 個所に集積され運用される．この時，CPU 間通信の通信速度の低さや，大きなレイテンシーが性能向上の妨げになっている．しかし，チップ上のネットワークオンチップであればスループットを増大させ，レイテンシーを低く保つことができることから，巨大なウエハースケール VLSI を用い，CPU 間通信をネットワークオンチップで担うことにできれば，スーパーコンピュータやデータセンターの性能を劇的に高めることが可能になる．しかし，ウエハー上には常に欠陥があるため，この実現には欠陥問題を解決する必要があった．そこで我々は故障があっても正常に動作できる光再構成アーキテクチャのウエハースケール VLSI への導入を検討している．本稿では，この光再構成アーキテクチャの詳細とそれを利用したウエハースケール VLSI の実現性について報告する．","subitem_description_type":"Other"}]},"item_4_description_8":{"attribute_name":"論文抄録(英)","attribute_value_mlt":[{"subitem_description":"When realizing a supercomputer or a data center, a number of CPUs are integrated. Current main concerns are long latency and low throughput of communication between CPUs. If a network on a chip with a short latency and a high throughput can be applied for the communications, the performance of supercomputers and data centers can be increased drastically. As an answer, we are considering a wafer-scale VLSI realization. However, since any wafer has defects, the realization is difficult. To solve the issue, we present a proposal of a new wafer-scale VLSI with optical reconfiguration architecture. In this paper, we report the details of the optical reconfiguration architecture and the feasibility of the wafer-scale VLSI using the architecture. ","subitem_description_type":"Other"}]},"item_4_biblio_info_10":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"4","bibliographic_titles":[{"bibliographic_title":"研究報告システムとLSIの設計技術（SLDM）"}],"bibliographicPageStart":"1","bibliographicIssueDates":{"bibliographicIssueDate":"2023-11-10","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"41","bibliographicVolumeNumber":"2023-SLDM-204"}]},"relation_version_is_last":true,"weko_creator_id":"44499"},"id":228908,"links":{}}